Memory hierarchy: Difference between revisions

Revision as of 22:27, 16 July 2006

Revision as of 15:29, 8 September 2006

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* [[Processor register]]s – fastest possible access (usually 1 CPU cycle), only hundreds of bytes in size

* Level 1 (L1) [[CPU cache|cache]] – often accessed in just a few cycles, usually tens of kilobytes

* Level 2 (L2) [[CPU cache|cache]] – higher latency than L1 by 2× to 10×, often 512KB512 [[KiB]] or more

* Level 3 (L3) [[CPU cache|cache]] – (optional) higher latency than L2, often multipleseveral MB's[[MiB]]

* [[Primary storage|Main memory]] ([[DRAM]]) – may take hundreds of cycles, but can be multiple gigabytes. Access times may not be uniform, in the case of a NUMA machine.

* [[Disk storage]] – hundreds of thousands of cycles latency, but very large

* [[Tertiary storage]] – tape, optical disk (WORM)

==Management ==

Modern [[programming language]]s mainly assume two levels of memory, main memory and disk storage, though directly accessing registers is allowable in rare cases. Programmers are responsible for moving data between disk and memory through file I/O. Hardware is in charge of moving data between memory and caches. Compilers are trying to optimize the usage of caches and registers.