Latency oriented processor architecture: Difference between revisions

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'''[[Latency (engineering)|Latency]] oriented processor architecture''' is the [[Microarchitecture|microarchitecture]] of a [[Microprocessor|microprocessor]] designed to serve a serial computing [[Thread (computing)|thread]] with a low latency. This is typical of most [[Central_processing_unit|Central Processing UnitsUnit]]s (CPU)]] being developed since the 1970s. These architectures, in general, aim to execute as many instructions as possible belonging to a single serial thread, in a given window of time; however, the time to execute a single instruction completely from fetch to retire stages may vary from a few cycles to even a few hundred cycles in some cases.<ref>{{cite book| author1=John Paul Shen, |author2=Mikko H. Lipasti (|year=2013). ''|title=Modern Processor Design''. |publisher=McGraw-Hill Professional. ISBN |isbn=1478607831}}</ref>{{page?}} Latency oriented processor architectures are the opposite of throughput-oriented processors which concern themselves more with the total [[Throughput|throughput]] of the system, rather than the service [[Latency (engineering)|latencies]] for all individual threads that they work on. <ref name=YanSohilin2016>{{cite book|author=Yan Solihin (|year=2016). ''|title=Fundamentals of Parallel Multicore Architecture''. |publisher=Chapman & Hall/CRC Computational Science. ISBNScienc |isbn=978-1482211184}}</ref> {{page?}}<ref name=GarlandKirk>{{cite journal|title=Understanding Throughput-Oriented Architectures by |author1=Michael Garland, |author2=David B. Kirk, |journal=Communications of the ACM, Vol. |volume=53 No. |number=11, Pages |pages=58-66}}</ref>

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'''[[Latency (engineering)|Latency]] oriented processor architecture''' is the [[Microarchitecture|microarchitecture]] of a [[Microprocessor|microprocessor]] designed to serve a serial computing [[Thread (computing)|thread]] with a low latency. This is typical of most [[Central_processing_unit|Central Processing Units (CPU)]] being developed since the 1970s. These architectures, in general, aim to execute as many instructions as possible belonging to a single serial thread, in a given window of time; however, the time to execute a single instruction completely from fetch to retire stages may vary from a few cycles to even a few hundred cycles in some cases.<ref>John Paul Shen, Mikko H. Lipasti (2013). ''Modern Processor Design''. McGraw-Hill Professional. ISBN 1478607831</ref> Latency oriented processor architectures are the opposite of throughput-oriented processors which concern themselves more with the total [[Throughput|throughput]] of the system, rather than the service latencies for all individual threads that they work on. <ref name=YanSohilin2016>Yan Solihin (2016). ''Fundamentals of Parallel Multicore Architecture''. Chapman & Hall/CRC Computational Science. ISBN 978-1482211184</ref> <ref name=GarlandKirk>Understanding Throughput-Oriented Architectures by Michael Garland, David B. Kirk, Communications of the ACM, Vol. 53 No. 11, Pages 58-66</ref>

==[[Flynn's taxonomy]]==