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==Implementation techniques==
There are many architectural techniques employed to reduce the overall latency for a single computing task. These typically involve adding additional hardware in the [[Pipeline_(computing)|pipeline]] to serve instructions as soon as they are fetched from [[Random-access_memory|memory]] or [[CPU cache|instruction cache]]. A notable characteristic of these architectures is that a significant area of the chip is used up in parts other than the [[Execution_unit|Execution Units]] themselves. This is because the intent is to bring down the time required to complete a 'typical' task in a computing environment. A typical computing task is a serial set of instructions, where there is a high dependency on results produced by the previous instructions of the same task. Hence, it makes sense that the microprocessor will be spending its time doing many other tasks other than the calculations required by the individual instructions themselves. If the [[Hazard_(computer_architecture)|hazards]] encountered during computation are not resolved quickly, then latency for the thread increases. This is because hazards stall execution of subsequent instructions and, depending upon the pipeline implementation, may either stall progress completely until the dependency is resolved or lead to an avalanche of more hazards in future instructions; further exacerbating execution time for the thread.<ref name="quant">{{cite book|author1=John L. Hennessy
The design space of micro-architectural techniques is very large. Below are some of the most commonly employed techniques to reduce the overall latency for a thread.
===Instruction set architecture (ISA)===
Most architectures today use shorter and simpler instructions, like the [[load/store architecture]], which help in optimizing the instruction pipeline for faster execution. Instructions are usually all of the same size which also helps in optimizing the instruction fetch logic. Such an ISA is called a [[Reduced instruction set computing|RISC]] architecture.<ref> Dileep Bhandarkar, Douglas W. Clark, ''Performance from architecture: comparing a RISC and a CISC with similar hardware organization'', ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, Pages 310-319</ref>
===Instruction Pipelining===
Pipelining overlaps execution of multiple instructions from the same executing thread in order to increase clock frequency or to increase the number of instructions that complete per unit time; thereby reducing the overall execution time for a thread. Instead of waiting for a single instruction to complete all its execution stages, multiple instructions are processed simultaneously, at their respective stages inside the pipeline. {{efn|''Computer Organization and Design: The Hardware/software Interface'', Chapter 4<ref name="interface"/>}}
===Register-renaming===
This technique is used to effectively increase the total register file size than that specified in the ISA to programmers, and to eliminate false dependencies. Suppose we have two consecutive instructions which reference the same register. The first reads the register while the second writes to it. To maintain correctness of the program, it is essential to make sure that the second instruction does not write to the register before the first can read its original value. This is an example of a [[WAR|Write-After-Read (WAR)]] dependency. To eliminate this dependency, the pipeline would 'rename' the instruction internally by assigning it to an internal register. The instruction is therefore allowed to execute and results produced by it will now be immediately available to all subsequent instructions, even though the actual destination register intended by the program will be written to later. Similarly if both the instructions simply meant to write to the same register [[WAW|Write-After-Write (WAW)]], the pipeline would rename them and ensure that their results are available to future instructions without the need to serialize their execution. {{efn|''Computer Architecture: A Quantitative Approach'', Section 3.1<ref name="quant"/>}}
===Memory Organization===
The different levels of memory, which includes [[Cache (computing)|caches]], [[main memory]] and [[non-volatile storage]] like hard disks (where the program instructions and data reside), are designed to exploit [[Locality of reference|spatial locality]] and [[temporal locality]] to reduce the total [[memory access time]]. The less time the processor spends waiting for data to be fetched from memory, the lower number of instructions consume pipeline resources while just sitting idle and doing no useful work. The instruction pipeline will be completely stalled if all it's internal buffers (for example [[Reservation station|reservation stations]]) are filled to their respective capacities. Hence, if instructions consume less number of idle cycles while inside the pipeline, there is a greater chance of exploiting [[Instruction level parallelism]] (ILP) as the fetch logic can pull in greater number of instructions from the cache/memory per unit time. {{efn|''Computer Organization and Design: The Hardware/software Interface'', Chapter 5<ref name="interface"/>}}
===Speculative Execution===
A major cause for pipeline stalls are control flow dependencies, i.e. when the outcome of a branch instruction is not known in advance (which is usually the case). Many architectures today use branch predictor components to guess the outcome of a branch. Execution continues along the predicted path for the program but instructions are tagged as speculative. If the guess turns out to be correct, then the instructions are allowed to complete successfully and to update their results back to register file/memory. If the guess was incorrect, then all speculative instructions are flushed from the pipeline and execution (re)starts along the actual correct path for the program. By maintaining a high prediction accuracy, the pipeline is able to significantly increase throughput for the executing thread. {{efn|''Computer Architecture: A Quantitative Approach'', Section 3.3<ref name="quant"/>}}
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===Superscalar Execution===
A super-scalar instruction pipeline pulls in multiple instructions in every clock cycle, as opposed to a simple scalar pipeline. This increases [[Instruction level parallelism]] (ILP) as many times as the number of instructions fetched in each cycle, except when the pipeline is stalled due to data or control flow dependencies. Even though the retire rate of superscalar pipelines is usually less than their fetch rate, the overall number of instructions executed per unit time (> 1) is generally greater than a scalar pipeline. {{efn|''Computer Architecture: A Quantitative Approach'', Sections 3.6-3.8<ref name="quant"/>}}
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