Latency oriented processor architecture: Difference between revisions

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===Instruction set architecture (ISA)===
{{Main article|Instruction set}}
Most architectures today use shorter and simpler instructions, like the [[load/store architecture]], which help in optimizing the instruction pipeline for faster execution. Instructions are usually all of the same size which also helps in optimizing the instruction fetch logic. Such an ISA is called a [[Reduced instruction set computing|RISC]] architecture.<ref>{{cite Dileep conference|last1=Bhandarkar, |first1=Dileep|last2=Clark|first2=Douglas W. Clark, ''|title=Performance from architectureArchitecture: comparingComparing a RISC and a CISC with similarSimilar hardware organization'', ASPLOS IVHardware Organization|journal=Proceedings of the fourthFourth internationalInternational conferenceConference on Architectural supportSupport for programmingProgramming languagesLanguages and operatingOperating systems,Systems|date=1 PagesJanuary 310-3191991|pages=310–319|doi=10.1145/106972.107003|url=http://dl.acm.org/citation.cfm?id=107003&CFID=860927590&CFTOKEN=39315780|publisher=ACM}}</ref>
 
===Instruction Pipelining===