Latency oriented processor architecture: Difference between revisions

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==Contrast with Throughput oriented processor architectures==
In contrast, a [[Throughput|throughput]] oriented processor architecture is designed to maximize the amount of 'useful work' done in a significant window of time. Useful work refers to large calculations on a significant amount of data. They do this by parallelizing the work load so that many calculations can be performed simultaneously. The calculations may belong to a single task or a limited number of multiple tasks. The total time required to complete 1 execution is significantly larger than that of a latency oriented processor architecture, however, the total time to complete a large set of calculations is significantly reduced. Latency is often sacrificed in order to achieve a higher throughput per cycle. <ref name=GarlandKirk/> As a result, a latency oriented processor may complete a single calculation significantly faster than a throughput-oriented processor; however, the throughput-oriented processor could be partway through hundreds of such computations by the time the latency oriented processor completes 1 calculation. <ref name=YanSohilin2016/>
 
Latency oriented processors expend a substantial chip area on sophisticated control structures like branch prediction, [[Operand forwarding|data forwarding]], [[Re-order buffer|re-order buffer]], large register files and caches in each processor. These structures help reduce operational latency and memory-access time per instruction, and make results available as soon as possible. Throughput oriented architectures on the other hand, usually have a multitude of processors with much smaller caches and simpler control logic. This helps to efficiently utilize the memory bandwidth and increase total the number of total number of execution units on the same chip area. <ref name=GarlandKirk/>
 
[[Graphics processing unit|GPUs]] are a typical example of throughput oriented processor architectures.