Latency oriented processor architecture: Difference between revisions

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===Register-renaming===
{{Main article|Register renaming}}
This technique is used to effectively increase the total register file size than that specified in the ISA to programmers, and to eliminate false dependencies. Suppose we have two consecutive instructions which reference the same register. The first reads the register while the second writes to it. To maintain correctness of the program, it is essential to make sure that the second instruction does not write to the register before the first can read its original value. This is an example of a [[WAR|Write-After-Read (WAR)]] dependency. To eliminate this dependency, the pipeline would 'rename' the instruction internally by assigning it to an internal register. The instruction is therefore allowed to execute and results produced by it will now be immediately available to all subsequent instructions, even though the actual destination register intended by the program will be written to later. Similarly if both the instructions simply meant to write to the same register [[WAWdata dependency|Write-After-Write (WAW)]], the pipeline would rename them and ensure that their results are available to future instructions without the need to serialize their execution. {{efn|''Computer Architecture: A Quantitative Approach'', Section 3.1<ref name="quant"/>}}
 
===Memory Organization===
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===Out-of-order execution===
{{Main article|Out-of-order execution}}
Not all instructions in a thread take the same amount of time to execute. Superscalar pipelines usually have multiple possible paths for instructions depending upon current state and the instruction type itself. Hence, to increase [[IPC|instructions per cycle]] (IPC) the pipeline allows execution of instructions out-of-order so that instructions later in the program are not stalled due to an instruction which will take longer to complete. All instructions are registered in a re-order buffer when they are fetched by the pipeline and allowed to retire (i.e. write back their results) in the order of the original program so as to maintain correctness. {{efn|''Computer Architecture: A Quantitative Approach'', Sections 3.4, 3.5<ref name="quant"/>}}
 
===Superscalar Execution===