Design for testing: Difference between revisions

Revision as of 18:49, 27 August 2006

Revision as of 22:23, 11 September 2006

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== Debug using DFT features ==

In addition to being useful for manufacturing "go/no go" testing, scan chains can also used to "debug" chip designs. In this context, the chip is exercised in normal "functional mode" (for example, a computer or mobile-phone chip might execute assembly language instructions). At any time, the chip clock can be stopped, and the chip re-configured into "test mode". At this point the full internal state can dumped out, or set to any desired values, by use of the scan chains. ThisAnother use of scan chains,to alongaid withdebug theconsists clockof controlscanning circuitsin thatan allowinitial thestate to all memory elements and then go clocksback to befunctional stoppedmode simultaneouslyto perform system debug. The advantage is to freezebring the system to a known state without going through many clock cycles. This use of scan chains, along with the chipclock --control circuits are a related sub-discipline of logic design called "Design for Debug" or "Design for Debugability".

== See also ==