XCore Architecture: Difference between revisions

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The '''XCore XS1Architecture''' is a 32-bit RISC microprocessor architecture designed by [[XMOS]]. The architecture is designed to be used in [[multi-core processor]]s for [[embedded system]]s. Each XS1 coreXCore executes up to eight concurrent threads, each thread having its own register set, and the architecture directly supports inter-thread and inter-core communication and various forms of thread scheduling.<ref>{{cite web

Two versions of the XCore architecture exist: the XS1 architecture <ref>{{cite web

|title=XMOS XS1 Architecture

|format=PDF
|date=07-12-2011

|url=https://www.xmos.com/download/final/The-XMOS-XS1-Architecture%28X7879A%29.pdf

|publisher=[[XMOS]]}}</ref> and the XS2 architecture. <ref>{{cite web

|title=XMOS XS2 Architecture

|format=PDF

|date=2016-12-21

|url=https://www.xmos.com/published/the-xmos-xs1-architecture

|publisher=[[XMOS]]}}</ref>

Processors with thisthe XS1 architecture include the [[XCore XS1-G4]] and [[XCore XS1-L1]]. Processors with the XS2 architecture include [[xCORE200]].

The architecture encodes instructions compactly, using 16 bits for frequently used instructions (with up to three operands) and 32 bits for less frequently used instructions (with up to 6 operands). Almost all instructions execute in a single cycle, and the architecture is event-driven in order to decouple the timings that a program needs to make from the execution speed of the program. A program will normally perform its computations and then wait for an [[Event (computing)|event]] (e.g. a [[Message passing|message]], time, or external I/O event) before continuing.

Processors with this architecture include the [[XCore XS1-G4]] and [[XCore XS1-L1]].

==Architecture==