XCore Architecture: Difference between revisions

Revision as of 17:36, 21 December 2016

Revision as of 17:45, 21 December 2016

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|title=XMOS XS1 Architecture

|format=PDF

|date=072016-12-201121

|url=https://www.xmos.com/downloadpublished/final/The-XMOSxmos-XS1xs1-Architecture%28X7879A%29.architecture?format=pdf

|publisher=[[XMOS]]}}</ref> and the XS2 architecture. <ref name='xs2'>{{cite web

|title=xCORE-200: The XMOS XS2 Architecture

|format=PDF

|date=2016-12-21

|url=https://www.xmos.com/published/thexs2-xmosisa-xs1-architecturespecification

|publisher=[[XMOS]]}}</ref>

Processors with the XS1 architecture include the [[XCore XS1-G4]] and [[XCore XS1-L1]]. Processors with the XS2 architecture include [[xCORE200xCORE-200]].

The architecture encodes instructions compactly, using 16 bits for frequently used instructions (with up to three operands) and 32 bits for less frequently used instructions (with up to 6 operands). Almost all instructions execute in a single cycle, and the architecture is event-driven in order to decouple the timings that a program needs to make from the execution speed of the program. A program will normally perform its computations and then wait for an [[Event (computing)|event]] (e.g. a [[Message passing|message]], time, or external I/O event) before continuing.

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The XS1 instruction set is implemented by the [[XCore XS1-G4]], [[XCore XS1-L1]], [[XCore XS1-SU]], and [[XCore XS1-AnA]]. The former is a four-core processing node, the latter three are single and dual core processing nodes.

The XS2 instruction set is implemented by the [[xCORE200xCORE-200]] series processors, which is marketed as the XL2 series (general purpose), XU2 series (USB), XE2 series (RGMII), and versions with embedded flash.

== References ==