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===XS2===
The XS2 architecture was defined in 2014, and extends the XS1 architecture with a limited form of [[Dual Issue]] execution <ref name='xs2'/>. The processor core comprises two lanes. The ''Resource lane'' can execute IO operations and general arithmetic. The ''Memory lane'' can execute memory operations, branches, and general arithmetic. Short resource or arithmetic instructions can be executed in the resource lane; short memory, branch, or arithmetic operations can be executed in the memory lane. Long instructions span both lanes.
In dual issue mode all pairs of instructions are aligned on a 32-bit boundary.
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