XCore Architecture: Difference between revisions

Revision as of 17:48, 21 December 2016

Revision as of 17:50, 21 December 2016

Line 5:

| introduced = 2007

| version = XS1

| design = [[RISC]]

| type = [[Load-store architecture|Load-store]]

| encoding = Variable

| branching = Condition register

| endianness = Little

| gpr = 12

| fpr = 0

}}

{{Infobox CPU architecture

| name = XCore

| designer = [[XMOS]]

| bits = 32-bit

| introduced = 2015

| version = XS2

| design = [[RISC]]

| type = [[Load-store architecture|Load-store]]

Line 171 ⟶ 185:

===XS1===

The XS1 architecture was the first xCORE architecture, defined in 20082007.

===XS2===

The XS2 architecture was defined in 20142015, and extends the XS1 architecture with a limited form of [[Dual Issue]] execution <ref name='xs2'/>. The processor core comprises two lanes. The ''Resource lane'' can execute IO operations and general arithmetic. The ''Memory lane'' can execute memory operations, branches, and general arithmetic. Short resource or arithmetic instructions can be executed in the resource lane; short memory, branch, or arithmetic operations can be executed in the memory lane. Long instructions span both lanes.

In dual issue mode all pairs of instructions are aligned on a 32-bit boundary.