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The architecture encodes instructions compactly, using 16 bits for frequently used instructions (with up to three operands) and 32 bits for less frequently used instructions (with up to 6 operands). Almost all instructions execute in a single cycle, and the architecture is event-driven in order to decouple the timings that a program needs to make from the execution speed of the program. A program will normally perform its computations and then wait for an [[Event (computing)|event]] (e.g. a [[Message passing|message]], time, or external I/O event) before continuing.
==Versions==▼
There are two versions of the xCORE architecture: XS1 and XS2; XS2 extending the XS1 architecture.
===XS1===▼
The XS1 architecture was the first xCORE architecture, defined in 2007.▼
===XS2===▼
The XS2 architecture was defined in 2015, and extends the XS1 architecture with a limited form of [[Dual Issue]] execution.<ref name='xs2'/> The processor core comprises two lanes. The ''Resource lane'' can execute IO operations and general arithmetic. The ''Memory lane'' can execute memory operations, branches, and general arithmetic. Short resource or arithmetic instructions can be executed in the resource lane; short memory, branch, or arithmetic operations can be executed in the memory lane. Long instructions span both lanes.▼
In dual issue mode all pairs of instructions are aligned on a 32-bit boundary.▼
==Architecture==
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Common resources that are supported are ports (for external input and output), timers (that allow timing to a reference clock), channels (that allow communication and synchronization between threads within a core, and threads on different cores), locks (which allow controlled access to shared memory), and synchronizers (which implement barrier synchronizations between threads).
▲==Versions==
▲===XS1===
▲The XS1 architecture was the first xCORE architecture, defined in 2007.
▲===XS2===
▲The XS2 architecture was defined in 2015, and extends the XS1 architecture with a limited form of [[Dual Issue]] execution.<ref name='xs2'/> The processor core comprises two lanes. The ''Resource lane'' can execute IO operations and general arithmetic. The ''Memory lane'' can execute memory operations, branches, and general arithmetic. Short resource or arithmetic instructions can be executed in the resource lane; short memory, branch, or arithmetic operations can be executed in the memory lane. Long instructions span both lanes.
▲In dual issue mode all pairs of instructions are aligned on a 32-bit boundary.
==Devices==
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