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* UMA using bus-based [[symmetric multiprocessing]] (SMP) architectures;
* UMA using [[crossbar switch]]es;
*pacifique memory access
==hUMA==
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Line 6:
* UMA using bus-based [[symmetric multiprocessing]] (SMP) architectures;
* UMA using [[crossbar switch]]es;
*pacifique memory access
==hUMA==
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