Revision as of 11:03, 28 December 2016 edit Henk.muller (talk \| contribs) 456 edits m →References ← Previous edit		Revision as of 11:04, 28 December 2016 edit undo Henk.muller (talk \| contribs) 456 edits m →XS2: added xCORE-VOICE implementation Next edit →
Line 55: ===XS2=== The XS2 architecture was defined in 2015. It is implemented by the [[xCORE-VOICE]] processors and [[xCORE-200]] series processors,. The ~~which~~latter isare marketed as the XL2 series (general purpose), XU2 series (USB), XE2 series (RGMII), and versions with embedded flash. XS2 extends the XS1 architecture with a limited form of [[Dual Issue]] execution.<ref name='xs2'/> The processor core comprises two lanes. The ''Resource lane'' can execute IO operations and general arithmetic. The ''Memory lane'' can execute memory operations, branches, and general arithmetic. Short resource or arithmetic instructions can be executed in the resource lane; short memory, branch, or arithmetic operations can be executed in the memory lane. Long instructions span both lanes. In dual issue mode all pairs of instructions are aligned on a 32-bit boundary.

XCore Architecture: Difference between revisions