Latency oriented processor architecture: Difference between revisions

Revision as of 05:09, 25 December 2016

Revision as of 19:01, 5 January 2017

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===Memory Organization===

{{Main article|Memory hierarchy}}

The different levels of memory, which includes [[Cache (computing)|caches]], [[main memory]] and [[non-volatile storage]] like hard disks (where the program instructions and data reside), are designed to exploit [[Locality of reference|spatial locality]] and [[temporal locality]] to reduce the total [[memory access time]]. The less time the processor spends waiting for data to be fetched from memory, the lower number of instructions consume pipeline resources while just sitting idle and doing no useful work. The instruction pipeline will be completely stalled if all it'sits internal buffers (for example [[reservation station]]s) are filled to their respective capacities. Hence, if instructions consume less number of idle cycles while inside the pipeline, there is a greater chance of exploiting [[Instruction level parallelism]] (ILP) as the fetch logic can pull in greater number of instructions from the cache/memory per unit time. {{efn|''Computer Organization and Design: The Hardware/software Interface'', Chapter 5<ref name="interface"/>}}

===Speculative Execution===