Automatic test pattern generation: Difference between revisions

Content deleted Content added
mNo edit summary
Line 35:
* Gate delay fault
* Transition fault
* Hold Time fault
* Slow/Small delay fault
* Path delay fault: This fault is due to the sum of all gate propagation delays along a single path. This fault shows that the delay of one or more paths exceeds the clock period. One major problem in finding delay faults is the number of possible paths in a circuit under test (CUT), which in the worst case can grow exponentially with the number of lines ''n'' in the circuit.