In the [[electronic design automation|automated]] design of [[integrated circuit]]s, '''signoff''' (also written as '''sign-off''') checks is the collective name given to a series of verification steps that the design must pass before the designit can be [[tapeout|taped out]]. This implies an iterative process involving incremental fixes across the board inusing one or more check typetypes, and then retesting the design. There are two types of sign-off's: are there,namely Front[[front-end sign-off]] and Back[[back-end sign-off]]. After back-end sign-off the chip will gogoes to Fabricationfabrication. After listing out all the features ofin the specification, Verificationthe Engineerverification engineer will write coverage for those features andto finds outidentify bugs, and sendssend back the RTL design to the designer. Bugs meansor missingdefects, ofcan include missing features (comparing the layout to the specification), errors in design (typo and functional errors)etc., etc. When the coverage reaches a maximum% then Verificationthe verification team will sign it off. Basically byBy using a methodology like UVM, OVM, or VMM, the verification team will developdevelops a reusable environment. Nowadays, UVM is getting more popular than others.
== Check types ==
Signoff checks have become more complex as [[VLSI]] designs approach [[22nm]] and below process nodes, because of the increased impact of previously ignored (or more crudely approximated) second-order effects. There are several categories of signoff checks.
* [[Design rule checking|DRC]] – Also sometimes known as geometric verification, this involves verifying if the design can be reliably [[semiconductor fabrication|manufactured]] given current photolithography limitations. In advanced process nodes, [[Design for manufacturability (IC)|DFM]] rules are upgraded from optional (for better yield) to required.
