Revision as of 07:14, 21 April 2017 edit 50504F (talk \| contribs) Extended confirmed users 548 edits Contents WP:SPLIT from MIPS instruction set		Revision as of 07:18, 21 April 2017 edit undo 50504F (talk \| contribs) Extended confirmed users 548 edits No edit summary Next edit →
Line 1: {{Main\|MIPS instruction set}} Since 1985, numerous processors implementing some version of the [[MIPS architecture]] have been designed and widely used. ==MIPS microprocessors== Line 134 ⟶ 136: * MIPS P5600 multiprocessor core (MIPS32 Release 5):<ref>{{Cite web\|url=https://imgtec.com/mips/warrior/p-class-p5600-multiprocessor-core/\|title=P-Class P5600 Multiprocessor Core - Imagination Technologies\|website=Imagination Technologies\|language=en-GB\|access-date=2016-06-22}}</ref> hardware virtualization with hardware table walk, 128-bit SIMD, 40-bit eXtended Physical Addressing (XPA) * MIPS P6600 multiprocessor core (MIPS64 Release 6): hardware virtualization with hardware table walk, 128-bit SIMD ==References== {{reflist}} ==See also== * [[List of MIPS architecture processors]] [[Category:MIPS Technologies]]

MIPS architecture processors: Difference between revisions