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== History ==
=== RISC pioneer ===
In 1981, a team led by [[John L. Hennessy]] at [[Stanford University]] started work on what would become the first MIPS processor. The basic concept was to increase performance through the use of deep [[instruction pipeline]]s. Pipelining as a basic technique was well known before (see [[IBM 801]] for instance). CPUs are built up from a number of dedicated sub-units such as instruction decoders, [[Arithmetic logic unit|ALUs]] (integer arithmetics and logic), [[load/store architecture|load/store]] units (handling memory), and so on. In a non-pipelined design, a particular instruction in a program sequence must be (almost) completed before the next can be issued for execution; in a pipelined architecture, successive instructions can instead overlap in execution.
One major barrier to pipelining was that some instructions, like division, take longer to complete and the CPU therefore has to wait before passing the next instruction into the pipeline. One solution to this problem is to use a series of interlocks that allows stages to indicate that they are busy, pausing the other stages upstream. Hennessy's team viewed these interlocks as a major performance barrier since they had to communicate to all the modules in the CPU which takes time, and appeared to limit the [[clock speed]]. A major aspect of the MIPS design was to fit every sub-phase, including cache-access, of all instructions into one cycle, thereby removing any needs for interlocking, and permitting a single cycle throughput.
Although this design eliminated a number of useful instructions such as multiply and divide it was felt that the overall performance of the system would be dramatically improved because the chips could run at much higher clock rates. This ramping of the speed would be difficult with interlocking involved. The elimination of these instructions became a contentious point.
The other difference between the MIPS design and the competing [[Berkeley RISC]] involved the handling of [[subroutine]] calls. RISC used a technique called [[register window]]s to improve performance of these very common tasks. Each subroutine call required its own set of registers, which in turn required more real estate on the CPU and more complexity in its design. Hennessy felt that a careful compiler could find free registers without resorting to a hardware implementation, and that simply increasing the number of registers would not only make this simple, but increase the performance of all tasks.
In other ways the MIPS design was very much a typical RISC design. To save bits in the instruction word, RISC designs reduce the number of instructions to encode. The MIPS design uses 6 bits of the 32-bit word for the basic opcode;<ref>[[Morgan Kaufmann Publishers]], ''Computer Organization and Design'', [[David Patterson (scientist)|David A. Patterson]] & [[John L. Hennessy]], Edition 3, ISBN 1-55860-604-1, page 63</ref> the rest may contain a single 26-bit jump address or it may have up to four 5-bit fields specifying up to three registers plus a shift value combined with another 6-bits of opcode; another format, among several, specifies two registers combined with a 16-bit immediate value, etc. This allowed the CPU to load up the instruction and the data it needed in a single cycle, whereas an (older) non-RISC design, such as the [[MOS Technology 6502]] for instance, required separate cycles to load the opcode and the data. This was one of the major performance improvements that RISC offered. However, modern non-RISC designs achieve this speed by other means (such as queues in the CPU).
=== First hardware ===
In 19841981, [[John L. Hennessy]] wasbegan the [[Stanford MIPS|MIPS]] (''Microprocessor without Interlocked Pipeline Stages'') project at [[Stanford University]] to investigate [[RISC]] technology. The results of his research convinced him of the future commercial potential of the designtechnology, and leftin Stanford1984, he took a sabbatical to formfound [[MIPS Computer Systems]]. TheyThe releasedcompany theirdesigned a new architecture that was also called [[MIPS architecture|MIPS]], and introduced the first designMIPS implementation, the '''[[R2000 (microprocessor)|R2000]]''', in 1985. The R2000 was improved, improvingand the design was introduced as the '''[[R3000]]''' in 1988. These 32-bit CPUs formed the basis of their company through the 1980s, used primarily in [[Silicon Graphics|SGI]]'s series of [[workstation]]s and later [[Digital Equipment Corporation]] DECstation workstations and servers. The SGI commercial designs deviated from the Stanford academic researchMIPS by implementing most of the interlocks in hardware, supplying full multiply and divide instructions (among others). The designs were guided, in part, by software architect [[Earl Killian (engineer)|Earl Killian]] who designed the MIPS III 64-bit instruction-set extension, and led the work on the R4000 microarchitecture.<ref name=twsNovZ23>{{cite news
|title= Earl Killian
|publisher= ''Paravirtual''
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