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The R2000 also had support for up to four co-processors, one of which was built into the main CPU and handled exceptions, traps and memory management, while the other three were left for other uses. One of these could be filled by the optional '''R2010''' [[floating point unit|FPU]], which had thirty-two 32-bit registers that could be used as sixteen 64-bit registers for double-precision.
The '''[[R3000]]''' succeeded the R2000 in 1988, adding 32 KB (soon increased to 64 KB) caches for instructions and data, along with support for shared-memory [[multiprocessing]] in the form of a [[cache coherence]] protocol. While there were flaws in the R3000s multiprocessing support, it was successfully used in several successful multiprocessor computers. The R3000 also included a built-in [[Memory management unit|MMU]], a common feature on CPUs of the era. The R3000, like the R2000, could be paired with a '''[[R3010]]''' FPU. The R3000 was the first successful MIPS design in the marketplace, and eventually over one million were made. A speed-bumped version of the R3000 running up to 40 MHz, the '''[[R3000A]]''' delivered a performance of 32 [[Million instructions per second|VUPs (VAX Unit of Performance)]]. The MIPS [[R3000A]]-compatible '''[[R3051]]''' running at 33.8688 MHz was the processor used in the [[Sony]] [[PlayStation (console)|PlayStation]] though it didn't have FPU or MMU. Third-party designs include Performance Semiconductor's '''[[R3400]]''' and IDT's '''[[R3500]]''', both of them were R3000As with an integrated R3010 FPU. [[Toshiba]]'s '''[[R3900]]''' was a virtually first [[System-on-a-chip|SoC]] for the early [[handheld PC]]s that ran [[Windows CE]]. A [[radiation-hardened]] variant for space applications, the [[Mongoose-V]], is a R3000 with an integrated R3010 FPU.
The '''[[R4000]]''' series, released in 1991, extended MIPS to a full 64-bit architecture, moved the FPU onto the main die to create a single-chip microprocessor, and had a high clock frequency of 100 MHz at introduction. However, in order to achieve the clock frequency, the caches were reduced to 8 KB each and they took three cycles to access. The high operating frequencies were achieved through the technique of [[deep pipelining]] (called super-pipelining at the time). The improved '''R4400''' followed in 1993. It had larger 16 KB primary caches, largely bug-free 64-bit operation, and support for a larger L2 cache.
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