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Line 45: "Chaos Computing: ideas and implementations" William L. Ditto, K. Murali and S. Sinha, Philosophical Transactions of the Royal Society London A, (2007) {{doi\|10.1098/rsta.2007.2116}}. "Experimental realization of the fundamental NOR Gate using a chaotic circuit," K. Murali, Sudeshna Sinha and William L. Ditto Phys. Rev. E 68, 016205 (2003). {{doi\|10.1103/PhysRevE.68.016205}} "Implementation of NOR gate by a chaotic Chua’s circuit," K. Murali, Sudeshna Sinha and William L. Ditto, ~~Int.~~International J.Journal of Bifurcation and Chaos, Vol. 13, No. 9, pp. 1–4, (2003). {{doi\|10.1142/S0218127403008053}} "Fault tolerance and detection in chaotic Computers" M.R. Jahed-Motlagh, B. Kia, W.L. Ditto and S. Sinha, International Journal of Bifurcation and Chaos 17, 1955-1968(2007){{doi\|10.1142/S0218127407018142}} *"Chaos-based computation via Chua's circuit: parallel computing with application to the SR flip-flop"D. Cafagna, G. Grassi, International Symposium on Signals, Circuits and Systems, ISSCS 2005, Volume: 2, 749-752 (2005) {{doi\|10.1109/ISSCS.2005.1511349}}

Chaos computing: Difference between revisions