Dynamic frequency scaling: Difference between revisions

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{{Use dmy dates|date=January 2014}}

'''Dynamic frequency scaling''' (also known as '''CPU throttling''') is a technique in [[computer architecture]] whereby the [[Clock rate|frequency]] of a microprocessor can be automatically adjusted "on the fly" depending on the actual needs, to [[Power management integrated circuit|conserve power]] and reduce the amount of heat generated by the chip. Dynamic frequency scaling helps preserve battery on mobile devices<ref>"[https://www.academia.edu/4186102/A_survey_of_techniques_for_improving_energy_efficiency_in_embedded_computing_systems A survey of techniques for improving energy efficiency in embedded computing systems]", IJCAET, 2014 </ref> and decrease cooling cost and noise on [[Quiet PC|quiet computing settings]], or can kickbe inuseful as a security measure for overheated systems (e.g. after poor [[overclocking]]). Dynamic frequency scaling is used in all ranges of computing systems, ranging from mobile systems to data centers<ref>"[https://www.academia.edu/6982393/Power_Management_Techniques_for_Data_Centers_A_Survey Power Management Techniques for Data Centers: A Survey]", ORNL Technical Report, 2014 </ref> to reduce the power at the times of low workload.

== Functioning ==

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The dynamic power (''switching power'') dissipated per unit of time by a chip is ''C·V²·A·f'', where C is the [[capacitance]] being switched per clock cycle, V is [[voltage]], A is the Activity Factor<ref name="ActivityFactor">{{cite web | url = | title = Timing-aware power-optimal ordering of signals | author = K. Moiseev, A. Kolodny and S. Wimer | work = ACM Transactions on Design Automation of Electronic Systems, Volume 13 Issue 4, September 2008 | accessdate = 22 November 2013 }}</ref> indicating the average number of switching events undergone by the transistors in the chip (as a unitless quantity) and f is the switching frequency.<ref>{{Cite book|first=J. M.|last= Rabaey|title= Digital Integrated Circuits|publisher= Prentice Hall|year= 1996}}</ref>

Voltage is therefore the main determinant of power usage and heating.<ref>{{cite web|url=https://software.intel.com/en-us/blogs/2014/02/19/why-has-cpu-frequency-ceased-to-grow|author= Victoria Zhislina|date=2014-02-19|title=Why has CPU frequency ceased to grow?|publisher=Intel}}</ref> The voltage required for stable operation is determined by the frequency at which the circuit is clocked, and can be reduced if the frequency is also reduced.<ref>https://www.usenix.org/legacy/events/hotpower/tech/full_papers/LeSueur.pdf</ref> Dynamic power alone does not account for the total power of the chip, however, as there is also static power, which is primarily because of various leakage currents. Due to static power consumption and asymptotic execution time it has been shown that the energy consumption of a piece of software shows convex energy behavior, i.e., there exists an optimal CPU frequency at which energy consumption is minimal.<ref>{{cite journal | author = K. De Vogeleer| title = The Energy/Frequency Convexity Rule: Modeling and Experimental Validation on Mobile Devices |year=2014 | arxiv = 1401.4655|display-authors=etal}}</ref>

[[Subthreshold leakage|Leakage current]] has become more and more important as transistor sizes have become smaller and threshold voltage levels lower. A decade ago, dynamic power accounted for approximately two-thirds of the total chip power. The power loss due to leakage currents in contemporary CPUs and SoCs tend to dominate the total power consumption. In the attempt to control the leakage power, high-k metal-gates and power gating have been common methods.

[[Dynamic voltage scaling]] is another related power conservation technique that is often used in conjunction with frequency scaling, as the frequency that a chip may run at is related to the operating voltage.

The efficiency of some electrical components, such as voltage regulators, decreases with increasing temperature, so the power usage may increase with temperature. Since increasing power use may increase the temperature, increases in voltage or frequency may increase system power demands even further than the CMOS formula indicates, and vice versa.<ref>{{cite web | url = http://www.silentpcreview.com/article821-page5.html | title = Asus EN9600GT Silent Edition Graphics Card | author = Mike Chin | page = 5 | work = Silent PC Review | accessdate = 21 April 2008}}</ref><ref name="SPCRNewLevels">{{cite web | url = http://www.silentpcreview.com/article814-page1.html | title = 80 Plus expands podium for Bronze, Silver & Gold | author = MIke Chin | work = Silent PC Review | accessdate = 21 April 2008 }}</ref>

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Dynamic frequency scaling reduces the number of instructions a processor can issue in a given amount of time, thus reducing performance. Hence, it is generally used when the workload is not CPU-bound.

Dynamic frequency scaling by itself is rarely worthwhile as a way to conserve switching power. Saving the mosthighest possible amount of power requires dynamic voltage scaling too, because of the V² component and the fact that modern CPUs are strongly optimized for low power idle states. In most constant-voltage cases, it is more efficient to run briefly at peak speed and stay in a deep idle state for longer time (called "race to idle" or computational sprinting), than it is to run at a reduced clock rate for a long time and only stay briefly in a light idle state. However, reducing voltage along with clock rate can change those tradeoffs.

A related-but-opposite technique is [[overclocking]], whereby processor performance is increased by ramping the processor's (dynamic) frequency beyond the manufacturer's design specifications.