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==== x86 ====
{{Main|AES instruction set|Intel SHA extensions}}
The [[X86]] [[Computer architecture|architecture]], as a [[Complex instruction set computer|CISC (Complex Instruction Set Computer)]] Architecture, typically implements complex [[algorithms]] in hardware.<ref name="Oxford">{{cite web|url=https://www.cs.ox.ac.uk/teaching/materials17-18/ca/lecture03.pdf|title=x86-64 Instruction Set|publisher=[[University of Oxford]]|pages=1|date={{date|2017-04-18}}|access-date={{date|2018-01-24}}}}</ref><ref name="Stanford">{{cite web|url=https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/|access-date={{date|2018-01-24}}|title=RISC vs CISC|publisher=[[Stanford University]]}}</ref> Cryptographic algorithms are no exception. The x86 architecture implements significant components of the [[Advanced Encryption Standard|AES (Advanced Encryption Standard)]] algorithm,<ref name="Intel AES Instructions" /> which can be used by the [[NSA]] for [[Top Secret]] information.<ref>{{cite web|url=http://csrc.nist.gov/groups/ST/toolkit/documents/aes/CNSS15FS.pdf |title=National Policy on the Use of the Advanced Encryption Standard (AES) to Protect National Security Systems and National Security Information |author=Lynn Hathaway |date={{date|June 2003}}|format=PDF |access-date={{date|2011-02-15}}}}</ref> The architecture also includes support for the [[Secure Hash Algorithms|SHA]] Hashing Algorithms through the [[Intel SHA extensions]].<ref name="Intel AES Instructions" /> Whereas AES is a cipher, which is useful for encrypting documents, [[Hash function|Hashing]] is used for verification, such as of passwords (see [[PBKDF2]]).
==== ARM ====
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