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'''ATPG''' (acronym for both '''A'''utomatic '''T'''est '''P'''attern '''G'''eneration and '''A'''utomatic '''T'''est '''P'''attern '''G'''enerator) is an [[electronic design automation]] method/technology used to find an input (or test) sequence that, when applied to a [[digital circuit]], enables [[automatic test equipment]] to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. The generated patterns are used to test semiconductor devices after manufacture, or to assist with determining the cause of failure ([[failure analysis]]<ref>{{cite conference| last=Crowell| first=G| author2=Press, R.| title=Using Scan Based Techniques for Fault Isolation in Logic Devices| booktitle=Microelectronics Failure Analysis | pages= 132–8}}</ref>). The effectiveness of ATPG is measured by the number of modeled defects, or [[fault models]], detectable and by the number of generated patterns. These metrics generally indicate [[test quality]] (higher with more fault detections) and test application time (higher with more patterns). ATPG efficiency is another important consideration that is influenced by the fault model under consideration, the type of circuit under test ([[Scan chain|full scan]], synchronous sequential, or asynchronous sequential), the level of abstraction used to represent the circuit under test (gate, register-transfer, switch), and the required [[Fault coverage|test quality]].
== Basics
A defect is an error caused in a device during the manufacturing process. A fault model is a mathematical description of how a defect alters design behavior. The logic values observed at the device's primary outputs, while applying a test pattern to some device under test (DUT), are called the output of that test pattern. The output of a test pattern, when testing a fault-free device that works exactly as designed, is called the expected output of that test pattern. A fault is said to be ''detected'' by a test pattern if the output of that test pattern, when testing a device that has only that one fault, is different than the expected output. The ATPG process for a targeted fault consists of two phases: ''fault activation'' and ''fault propagation''. Fault activation establishes a signal value at the fault model site that is opposite of the value produced by the fault model. Fault propagation moves the resulting signal value, or fault effect, forward by sensitizing a path from the fault site to a primary output.
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Due to the high complexity of the sequential ATPG, it remains a challenging task for large, highly sequential circuits that do not incorporate any [[Design For Test]]ability (DFT) scheme. However, these test generators, combined with low-overhead DFT techniques such as [[partial scan]], have shown a certain degree of success in testing large designs. For designs that are sensitive to area or performance overhead, the solution of using sequential-circuit ATPG and partial scan offers an attractive alternative to the popular full-scan solution, which is based on combinational-circuit ATPG.
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Historically, ATPG has focused on a set of faults derived from a gate-level fault model. As design trends move toward nanometer technology, new manufacture testing problems are emerging. During design validation, engineers can no longer ignore the effects of crosstalk and power supply noise on reliability and performance. Current fault modeling and vector-generation techniques are giving way to new models and techniques that consider timing information during test generation, that are scalable to larger designs, and that can capture extreme design conditions. For nanometer technology, many current design validation problems are becoming manufacturing test problems as well, so new fault-modeling and ATPG techniques will be needed.
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* '''Wavelet Automatic Spectral Pattern Generator''' (WASP) is an improvement over spectral algorithms for sequential ATPG. It uses wavelet heuristics to search space to reduce computation time and accelerate the compactor. It was put forward by [[Suresh kumar Devanathan]] from Rake Software and Michael Bushnell, Rutgers University. [[Suresh kumar Devanathan]] invented WASP as a part of his thesis at Rutgers.
== Relevant
ATPG is a topic that is covered by several conferences throughout the year. The primary US conferences are the [http://www.itctestweek.org/ International Test Conference] and [http://www.tttc-vts.org/ The VLSI Test Symposium], while in Europe the topic is covered by [http://www.date-conference.com/ DATE] and [http://www.ieee-ets.org/ ETS].
== See also ==
* [[
* [[Design for test]] (DFT)
* [[Fault model]]
▲* [[Built-in self-test|Built-In Self-Test]] (BIST)
* [[JTAG]]
▲* [[Boundary Scan]] (BSCAN)
* [[VHSIC]]
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