Deep reactive-ion etching: Difference between revisions

Revision as of 10:34, 17 March 2018

Revision as of 18:26, 7 April 2018

Line 26:

* in MEMS, DRIE is used for anything from a few micrometers to 0.5 mm.

* in irregular chip dicing, DRIE is used with a novel hybrid soft/hard mask to achieve sub-millimeter etching to dice silicon dies into lego-like pieces with irregular shapes.<ref>{{cite journal | last1= Ghoneim | first1= Mohamed | last2 = Hussain | first2= Muhammad | title = Highly Manufacturable Deep (Sub-Millimeter) Etching Enabled High Aspect Ratio Complex Geometry Lego-Like Silicon Electronics| journal= small | date= 1 February 2017 | url = http://onlinelibrary.wiley.com/wol1/doi/10.1002/smll.201601801/full | doi=10.1002/smll.201601801 | volume=13 | page=1601801}}</ref><ref>{{cite news | last= Mendis | first= Lakshini | title= Lego-like Electronics | newspaper= Nature Middle East | date= 14 February 2017 | url=http://www.natureasia.com/en/nmiddleeast/article/10.1038/nmiddleeast.2017.34}}</ref><ref>{{cite news | last= Berger | first= Michael | title=Lego like silicon electronics fabricated with hybrid etching masks | newspaper= Nanowerk | date= 6 February 2017 | url= http://www.nanowerk.com/spotlight/spotid=45763.php}}</ref>

* in flexible electronics, DRIE is used to make tradition monolithic CMOS devices flexible by reducing the thickness of silicon substrates to few to tens of micrometers.<ref>{{ cite journal | last1= Ghoneim | first1= Mohamed | first2=Nasir | last2=Alfaraj | first3=Galo | last3=Torres-Sevilla | first4=Hossain | last4=Fahad | first5=Muhammad | last5=Hussain | title=Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS | journal=IEEE Transactions on Electron Devices | date= July 2016 | url=http://ieeexplore.ieee.org/abstract/document/7471458/ | doi=10.1109/ted.2016.2561239}}</ref><ref>{{ cite journal | first1= Mohamed T. | last1= Ghoneim | first2= Muhammad M. | last2= Hussain | title=Review on physically flexible nonvolatile memory for internet of everything electronics | journal= electronics | date=23 July 2015 | url= http://www.mdpi.com/2079-9292/4/3/424/htm}}</ref><ref>{{cite journal | first1= Mohamed T. | last1= Ghoneim | first2= Muhammad M. | last2= Hussain | title=Study of harsh environment operation of flexible ferroelectric memory integrated with PZT and silicon fabric | journal=Applied Physics Letters | date=3 August 2015 | url=http://aip.scitation.org/doi/abs/10.1063/1.4927913 | doi=10.1063/1.4927913 | volume=107 | page=052904}}</ref><ref>{{cite journal | first1=Mohamed T. | last1=Ghoneim | first2=Jhonathan P. | last2=Rojas | first3=Chadwin D. | last3=Young | first4=Gennadi | last4=Bersuker | first5=Muhammad M. | last5=Hussain | title=Electrical Analysis of High Dielectric Constant Insulator and Metal Gate Metal Oxide Semiconductor Capacitors on Flexible Bulk Mono-Crystalline Silicon | journal= IEEE Transactions on Reliability | date=26 November 2014 | url=http://ieeexplore.ieee.org/abstract/document/6967871/}}</ref><ref>{{cite journal | first1=Mohamed T. | last1=Ghoneim | first2=Mohammed A. | last2=Zidan | first3=Mohammed Y. | last3=Alnassar | first4=Amir N. | last4=Hanna | first5=Jurgen | last5= Kosel | first6=Khaled N. | last6=Salama | first7=Muhammad | last7=Hussain | title=Flexible Electronics: Thin PZT-Based Ferroelectric Capacitors on Flexible Silicon for Nonvolatile Memory Applications | journal=Advanced Electronic Materials | date=15 June 2015 | url=http://onlinelibrary.wiley.com/doi/10.1002/aelm.201500045/full | doi=10.1002/aelm.201500045 | volume=1 | page=1500045}}</ref><ref>{{cite journal | first1=Mohamed T. | last1=Ghoneim |first2=Arwa | last2=Kutbee | first3=Farzan | last3=Ghodsi | first4=G. |last4=Bersuker | first5=Muhammad M. | last5=Hussain | title=Mechanical anomaly impact on metal-oxide-semiconductor capacitors on flexible silicon fabric | journal= Applied Physics Letters | date=9 June 2014 | url=http://aip.scitation.org/doi/abs/10.1063/1.4882647 | doi=10.1063/1.4882647 | volume=104 | page=234104}}</ref>

What distinguishes DRIE from RIE is etch depth: Practical etch depths for RIE (as used in [[integrated circuit|IC]] manufacturing) would be limited to around 10&nbsp;µm at a rate up to 1&nbsp;µm/min, while DRIE can etch features much greater, up to 600&nbsp;µm or more with rates up to 20&nbsp;µm/min or more in some applications.