Pass transistor logic: Difference between revisions

Revision as of 11:24, 14 April 2018

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=={{anchor|CPL}}Complementary pass transistor logic==

Some authors use the term "complementary pass transistor logic" (CPL) to indicate a style of implementing logic gates that uses [[transmission gate]]s composed of both NMOS and PMOS pass transistors.<ref>

Gary K. Yeap.

[https://books.google.com/books?id=sXTdBwAAQBAJ "Practical Low Power Digital VLSI Design"].

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[https://books.google.com/books?id=VOnyWUUUj04C "Digital Design and Fabrication"].

p. 2-39.

</ref><ref name="IEEE_1990"/><ref name="ULVD_2015"/>

</ref>

Other authors use the term "complementary pass transistor logic" (CPL) to indicate a style of implementing logic gates using dual-rail encoding. Every CPL gate has two output wires, both the positive signal and the complementary signal, eliminating the need for inverters.<ref>

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==References==

{{Reflist|2}}refs=

<ref name="IEEE_1990">{{cite journal |title=A 3.8-ns CMOS 16x16-b multiplier using complementary pass-transistor logic |author-last1=Yano |author-first1=K. |author-last2=Yamanaka |author-first2=T. |author-last3=Nishida |author-first3=T. |author-last4=Saito |author-first4=M. |author-last5=Shimohigashi |author-first5=K. |author-last6=Shimizu |author-first6=A. |date=1990 |journal=[[IEEE Journal of Solid State Circuits]] |volume=25 |issue=2 |pages=388-395 |doi=10.1109/4.52161}}</ref>

<ref name="ULVD_2015">{{cite book |title=Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits |author-first1=Nele |author-last1=Reynders |author-first2=Wim |author-last2=Dehaene |series=Analog Circuits And Signal Processing (ACSP) |date=2015 |edition=1 |___location=Heverlec, Belgium |publisher=[[Springer International Publishing AG Switzerland]] |publication-place=Cham, Switzerland |isbn=978-3-319-16135-8 |issn=1872-082X |doi=10.1007/978-3-319-16136-5 |lccn=2015935431}}</ref>

}}

==Further reading==