Numerically controlled oscillator: Difference between revisions

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==Phase accumulator==

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A binary phase accumulator consists of an N-bit binary [[adder (electronics)|adder]] and a [[hardware register|register]] configured as shown in Figure 1.<ref name="Grzeg"/> Each clock cycle produces a new N-bit output consisting of the previous output obtained from the register summed with the frequency control word (FCW) which is constant for a given output frequency. The resulting output waveform is a staircase with step size <math>\Delta F</math>, the integer value of the FCW.<ref name="ADI"/> In some configurations, the phase output is taken from the output of the register which introduces a one clock cycle [[latency (engineering)|latency]] but allows the adder to operate at a higher clock rate.<ref name="latticeSC" />

[[Image:Phase Accum Graph.png|frame|Figure 2: Normalized phase accumulator output]]

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where W is the number of bits truncated.

In calculating the [[Spuriousspurious-free dynamic range]], we are interested in the spurious product with the largest amplitude relative to the carrier output level given by:

:<math>\zeta _{max}=2^{-M} \frac{\pi \mbox{GCD}(\Delta F,2^W)}{\sin \left( \pi \cdot 2^{-P}\mbox{GCD}(\Delta F,2^W) \right)}</math>

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===Amplitude truncation spurs===

Another source of spurious products is the amplitude [[Quantization (signal processing)|quantization]] of the sampled waveform contained in the PAC look up table(s). If the number of DAC bits is P, the

AM spur level is approximately equal to −6.02 &nbsp;P − 1.76 &nbsp;[[dBc]].<ref name="intersil">{{ cite web | title = The NCO as a Stable, Accurate Synthesizer | url = http://www.intersil.com/content/dam/Intersil/documents/tb31/tb318.pdf | id = TB318.1 | publisher = Intersil Corporation | year = 1998 }}</ref>

===Mitigation techniques===

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==See also==

* [[Direct digital synthesizer]] (DDS)

* [[Digitally controlled oscillator]] (DCO)

* [[Digital-to-analog converter]] (DAC)

==References==

{{reflist|2}}

{{good article}}