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Experimental work published in 2011 and 2012 demonstrates significantly greater speedups for advanced PRAM algorithms on XMT prototypes than for the same problems on state-of-the-art multi-core computers.
Work published in 2018 shows that lock-step parallel programming (using ICE) can achieve the same performance as the fastest hand-tuned multi-threaded code on XMT systems. Such inductive lock-step approach stands in contrast to multi-threaded programming approaches of other many core systems that are known for challenging programmers.
The XMT paradigm was introduced by [[Uzi Vishkin]].
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Experimental work reported in {{harvtxt|Caragea|Vishkin|2011}} for the [[Maximum flow problem]], and in two papers by {{harvtxt|Edwards|Vishkin|2012}} for the Graph Connectivity ([[Connectivity (graph theory)]]), Graph Biconnectivity ([[biconnected graph]]) and Graph Triconnectivity ([[Triconnected component]]) problems demonstrated that for some of the most advanced algorithms in the parallel algorithmic literature, the XMT paradigm can offer 8 times to over 100 times greater speedups than for the same problems on state-of-the-art multi-core computers. Each reported speedup was obtained by comparing clock cycles on an XMT prototype relative to the fastest serial algorithm running on the fastest serial machines.
XMT protoyping was culminated in {{harvtxt|Ghanim|Vishkin|Barua|2018}}, establishing that lock-step parallel programming (using ICE) can achieve the same performance as the fastest hand-tuned multi-threaded code on XMT systems. This 2018 result sharpens the contrast between XMT programming and the multi-threaded programming approaches employed by nearly all other many-core systems, whose race conditions and other demands tend to challenge, and sometimes even fail programmers.
==References==
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| doi=10.1145/2312005.2312042
}}.
*{{Citation
| last1=Ghanim | first1=Fady
| last2=Vishkin | first2=Uzi
| last3=Barua | first3=Rajeev
| journal= IEEE Transactions on Parallel and Distributed Systems
| volume=29
| issue=2
| date=February 2018
| title=Easy PRAM-Based High-Performance Parallel Programming with ICE
| pages=377–390
| doi=10.1109/TPDS.2017.2754376
}}.
==Notes==
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