Bus encoding: Difference between revisions

Revision as of 21:02, 8 July 2018

Revision as of 21:25, 8 July 2018

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<ref name="Shifted_Gray">{{cite journal |author-first1=Hui |author-last1=Guo |author-first2=Sri |author-last2=Parameswaran |doi=10.1016/j.sysarc.2010.03.003 |url=http://www.sciencedirect.com/science/article/pii/S1383762110000159 |volume=56 |issue=4–6 |date=April–June 2010 ||title=Shifted Gray encoding to reduce instruction memory address bus switching for low-power embedded systems |journal=Journal of Systems Architecture |pages=180–190}}</ref>

<ref name="Zero-Transition_1997">{{cite journal |author-first1=Luca |author-last1=Benini |author-first2=Giovanni |author-last2=De Micheli |author-first3=Enrico |author-last3=Macii |author-first4=D. |author-last4=Sciuto |author-first5=C. |author-last5=Silvano |title=Asymptotic Zero-Transition Activity Encoding for Address Buses in Low-Power Microprocessor-Based Systems |journal=Proceedings Seventh Great Lakes Symposium on VLSI |pages=77-82 |date=March 1997}}</ref>

<ref name="Stan_1995">{{cite journal |author-first1=M.Mircea R. |author-last1=Stan |author-first2=W.Wayne P. |author-last2=Burleson |title=Bus-invertInvert codingCoding for lowLow-powerPower I/O |publisherjournal=IEEE Transactions On Very Large Scale Integration (VLSI) Systems |volume=3 |number=1 |pages=49-58 |date=March 1995 |id=1063-8210/95$04.00 |url=http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.89.2154&rep=rep1&type=pdf |access-date=2018-07-08 |dead-url=no |archive-url=https://web.archive.org/web/20180708204233/http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.89.2154&rep=rep1&type=pdf |archive-date=2018-07-08}}</ref>

<ref name="Inversion">{{cite web |url=http://www.eng.auburn.edu/~agrawvd/COURSE/E6270_Fall07/PROJECT/JIANG/Low%20power%2032-bit%20bus%20with%20inversion%20encoding.ppt}}</ref>

<ref name="Yang">{{cite journal |author-first1=J. |author-last1=Yang |author2=et al. |title=FV encoding for low power data I/O |journal=ISLPED 2001 |date=August 2001 |pages=84-87}}</ref>