Direct memory access: Difference between revisions

Revision as of 02:42, 12 October 2018

Revision as of 02:43, 12 October 2018

Line 1:

[[File:AMD DirectGMA.svg|thumb|AMD DirectGMA is a form of DMA. It enables low-latency peer-to-peer data transfers between devices on the [[PCI Express|PCIe bus]] and [[AMD FirePro]]-branded products. [[Serial digital interface]] (SDI) devices supporting DirectGMA can write directly into the graphics memory of the GPU and vice versa the GPU can directly access the memory of a peer device.]] Used to access dma.

'''Direct memory access''' ('''DMA''') is a feature of computer systems that allows certain hardware subsystems to access main system [[computer storage|memory]] ([[random-access memory]]), independent of the [[central processing unit]] (CPU).

Line 115:

{{main|Cell (microprocessor)}}

As an example usage of DMA in a [[multiprocessor-system-on-chip]], IBM/Sony/Toshiba's [[Cell (microprocessor)|Cell processor]] incorporates a DMA engine for each of its 9 processing elemen tselements including one Power processor element (PPE) and eight synergistic processor elements (SPEs). Since the SPE's load/store instructions can read/write only its own local memory, an SPE entirely depends on DMAs to transfer data to and from the main memory and local memories of other SPEs. Thus the DMA acts as a primary means of data transfer among cores inside this [[central processing unit|CPU]] (in contrast to cache-coherent CMP architectures such as Intel's cancelled [[GPGPU|general-purpose GPU]], [[Larrabee (microarchitecture)|Larrabee]]).

DMA in Cell is fully [[#Cache coherency|cache coherent]] (note however local stores of SPEs operated upon by DMA do not act as globally coherent cache in the [[CPU cache|standard sense]]). In both read ("get") and write ("put"), a DMA command can transfer either a single block area of size up to 16 KB, or a list of 2 to 2048 such blocks. The DMA command is issued by specifying a pair of a local address and a remote address: for example when a SPE program issues a put DMA command, it specifies an address of its own local memory as the source and a virtual memory address (pointing to either the main memory or the local memory of another SPE) as the target, together with a block size. According to an experiment, an effective peak performance of DMA in Cell (3&nbsp;GHz, under uniform traffic) reaches 200 GB per second.<ref name="petrini-cell">{{cite web |first=Michael |last=Kistler |title=Cell Multiprocessor Communication Network |work=Extensive benchmarks of DMA performance in Cell Broadband Engine |date=May 2006|url=http://portal.acm.org/citation.cfm?id=1158825.1159067 }}</ref>