Routing (electronic design automation): Difference between revisions

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mentioned Bloodhound and Specctra routers, added refs
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* Gridless router<ref name="Whitaker_2005"/><ref name="Minges_1989"/>
** [[Area router]]
** Graph-theoretical router
*** [[Bloodhound router]]<ref name="CW_1992_Bloodhound"/><ref name="Pfeil_2017_Bloodhound"/><ref name="Redlich_2018_Routers"/> (CADStar)
*** [[Specctra]]<ref name="Redlich_2018_Routers"/> (aka [[Allegro PCB Router]])
** {{anchor|Topological router}}Topological router
*** [[FreeStyle Router]] (aka ''SpeedWay'', a [[DOS]]-based autorouter for [[P-CAD]])<!-- since 1997 (possibly 1991 or 1996) -->
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<ref name="Hadlock_1977">{{cite journal |author-first=Frank O. |author-last=Hadlock |title=A shortest path algorithm for grid graphs |journal=Networks |date=1977-12-01 |volume=7 |number=4 |pages=323-334 |doi=10.1002/net.3230070404 |url=https://www.researchgate.net/publication/227815552_A_Shortest_Path_Algorithm_for_Grid_Graphs}}</ref>
<ref name="SimplifyPCB">http://www.simplifyda.com</ref>
<ref name="Pfeil_2017_Bloodhound">{{cite journal |title=A lifetime designing PCBs: From design to software |author-first=Charles |author-last=Pfeil |date=2017-11-02 |journal=[[EDN Network]] |url=https://www.edn.com/electronics-blogs/all-aboard-/4459033/A-lifetime-designing-PCBs--From-design-to-software |access-date=2018-10-20 |dead-url=no |archive-url=https://web.archive.org/web/20181021225546/https://www.edn.com/electronics-blogs/all-aboard-/4459033/A-lifetime-designing-PCBs--From-design-to-software |archive-date=2018-10-20<!-- -->}}</ref>
<ref name="CW_1992_Bloodhound">{{cite web |title=Computer-Partner Kiel GmbH: "Bloodhound" entflechtet Leiterplatten auf 16 Lagen |language=German |journal=[[Computerwoche]] |date=1992-03-13 |url=https://www.computerwoche.de/a/bloodhound-entflechtet-leiterplatten-auf-16-lagen,1133225 |access-date=2018-10-20 |dead-url=no |archive-url=http://archive.is/0E57S |archive-date=2018-10-20}}</ref>
<ref name="Redlich_2018_Routers">{{cite book |title=Schaltungsdesign |author-first=Detlef |author-last=Redlich |chapter=1.6. Rechnergestützter Leiterplattenentwurf - Entflechtung |language=German |publisher=[[Ernst-Abbe-Hochschule Jena]] (EAH) |url=http://web.eah-jena.de/fhj/etit/fb/homepage/home-redlich/lehre/design/Documents/Rechnergest_LP_Entwurf_Einf%C3%BChrung.pdf |access-date=2018-10-20 |dead-url= |archive-url=http://archive.is/NeYMu |archive-date=2018-10-20}}</ref>
}}