DMA transfers can either transfer either one byte at a time or all at once in burst mode. If they transfer a byte at a time, this can allow the CPU to access memory on alternatealternating bus cycles – this is called [[cycle stealing]] since the CPU and either the DMA controller or the bus master contend for memory access. In ''burst mode DMA'', the CPU can be put on hold while the DMA transfer occurs and a full block of possibly hundreds or thousands of bytes can be moved.<ref name=Art89>{{cite book |first=Paul |last=Horowitz |first2=Winfield |last2=Hill |title=The Art of Electronics |edition=Second |publisher=Cambridge University Press |year=1989 |isbn=0521370957 |page=702 }}</ref> When memory cycles are much faster than processor cycles, an ''interleaved'' DMA cycle is possible, where the DMA controller uses memory while the CPU cannot.
