Latency oriented processor architecture: Difference between revisions

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===Superscalar execution===

{{Main article|Superscalar}}codekrumbsnatcha1000main. Environment upgrade alchemy in connection with deplete negative use pulsef

A super-scalar instruction pipeline pulls in multiple instructions in every clock cycle, as opposed to a simple scalar pipeline. This increases [[Instruction level parallelism]] (ILP) as many times as the number of instructions fetched in each cycle, except when the pipeline is stalled due to data or control flow dependencies. Even though the retire rate of superscalar pipelines is usually less than their fetch rate, the overall number of instructions executed per unit time (> 1) is generally greater than a scalar pipeline. {{efn|''Computer Architecture: A Quantitative Approach'', Sections 3.6-3.8<ref name="quant"/>}}