In the PEM model, there is no [[Computer network | direct communication network]] between the P processors. The processors have to communicate indirectly over the [[External memory algorithm |main memory]]. If multiple processors try to access the same block in [[External memory algorithm |main memory]] concurrently read/write conflicts<ref name=":0">{{Cite journal|last=Arge|first=Lars|last2=Goodrich|first2=Michael T.|last3=Nelson|first3=Michael|last4=Sitchinava|first4=Nodari|date=2008|title=Fundamental parallel algorithms for private-cache chip multiprocessors|url=http://dx.doi.org/10.1145/1378533.1378573|journal=Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures - SPAA '08|___location=New York, New York, USA|publisher=ACM Press|doi=10.1145/1378533.1378573|isbn=9781595939739}}</ref> occur. Like in the PRAM model, three different variations of this problem are considered:
*Concurrent Read Concurrent Write (CRCW): The same block in main memory can be read and written by multiple processors concurrently.
*Concurrent Read Exclusive Write (CREW): The same block in main memory can be read by multiple processors concurrently. Only one processor can write to a block at a time.
