Pass transistor logic: Difference between revisions

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In [[electronics]], '''pass transistor logic''' (PTL) describes several [[logic family|logic families]] used in the design of [[integrated circuit]]s. It reduces the count of transistors used to make different [[logic gate]]s, by eliminating redundant transistors. Transistors are used as switches to pass [[logic level]]s between nodes of a circuit, instead of as switches connected directly to supply voltages.<ref>Jaume Segura, Charles F. Hawkins ''CMOS electronics: how it works, how it fails'', Wiley-IEEE, 2004 {{ISBN|0-471-47669-2}}, page 132</ref> This reduces the number of active devices, but has the disadvantage that the difference of the voltage between high and low logic levels decreases at each stage. Each transistor in series is less saturated at its output than at its input.<ref>Clive Maxfield ''Bebop to the boolean boogie: an unconventional guide to electronics''Newnes, 2008 {{ISBN|1-85617-507-3}}, pp. 423-426</ref> If several devices are chained in series in a logic path, a conventionally constructed gate may be required to restore the signal voltage to the full value. By contrast, conventional [[CMOS logic]] switches transistors so the output connects to one of the power supply rails, so logic voltage levels in a sequential chain do not decrease.

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== Applications ==

[[Image:SRAM Cell (6 Transistors).svg|thumb|250px|A six-transistor CMOS [[Static random-access memory | SRAM ]] cell. M5 and M6 are bidirectional pass transistors.]]

[[Image:Multiplexer-based latch using transmission gates.svg|thumb|250px|a 10-transistor CMOS [[ flip-flop (electronics)#Gated D latch | gated D latch]], similar to the ones in the CD4042 or the CD74HC75 integrated circuits. ]]

Pass transistor logic often uses fewer transistors, runs faster, and requires less power than the same function implemented with the same transistors in fully complementary CMOS logic.<ref>

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</ref>

XOR has the worst-case [[Karnaugh map]]—if --implemented from simple gates, it requires more transistors

if implemented from simple gates, it requires more transistors

than any other function.

The designers of the [[Z80]] and many other chips saved a few transistors by implementing the

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</ref>

''Complementary pass transistor logic'' or "Differential pass transistor logic" refers to a [[logic families|logic family]] which is designed for certain advantage. It is common to use this logic family for [[Multiplexer#Digital multiplexers|multiplexers]] and [[Latch (electronics)|latches]].{{factcitation needed|date=April 2015}}

CPL uses series transistors to select between possible inverted output values of the logic, the output of which drives an [[Inverter (logic gate)|inverter]] The CMOS [[transmission gate]]s consist of nMOS and pMOS transistor connected in parallel.

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==References==

{{Reflist|refs=

<ref name="IEEE_1990">{{cite journal |title=A 3.8-ns CMOS 16x16-b multiplier using complementary pass-transistor logic |author-last1=Yano |author-first1=Kuniaki |author-last2=Yamanaka |author-first2=Toshiaki Yamanaka |author-last3=Nishida |author-first3=Takeshi |author-last4=Saito |author-first4=Mitsuo |author-last5=Shimohigashi |author-first5=Katsuhiro |author-last6=Shimizu |author-first6=Atsushi |date=1990 |journal=[[IEEE Journal of Solid -State Circuits]] |volume=25 |issue=2 |pages=388-395388–395 |doi=10.1109/4.52161}}</ref>

<ref name="ULVD_2015">{{cite book |title=Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits |author-first1=Nele |author-last1=Reynders |author-first2=Wim |author-last2=Dehaene |series=Analog Circuits And Signal Processing (ACSP) |date=2015 |edition=1 |___location=Heverlee, Belgium |publisher=[[Springer International Publishing AG Switzerland]] |publication-place=Cham, Switzerland |isbn=978-3-319-16135-8 |issn=1872-082X |doi=10.1007/978-3-319-16136-5 |lccn=2015935431}}</ref>

}}