Power Processing Element: Difference between revisions

Revision as of 11:47, 1 September 2018

Revision as of 06:07, 9 March 2019

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| variant = [[Cell (microprocessor)|Cell BE]], [[Xenon (processor)|XCPU]], [[Xenon (processor)#XCGPU|XCGPU]], [[Cell processor#PowerXCell 8i|PowerXCell 8i]]

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The Power Processing Unit (PPU) is a [[64-bit]] [[Multithreading (computer architecture)|dual threaded]] [[Out-of-order execution|in-order]] [[Power ArchitectureISA|Power ISA 2.03]] [[microprocessor]] [[Multi-core processor|core]] designed by [[IBM]] for use primarily in the [[game console]]s [[PlayStation 3]] and [[Xbox 360]], but has also found applications in high performance computing in [[supercomputer]]s such as the record setting [[IBM Roadrunner]].

In most instances the PPU is joined by a 512 KB L2 cache to form what is called the '''Power Processing Element''' (PPE).