Advanced Programmable Interrupt Controller: Difference between revisions

Revision as of 16:54, 18 March 2019

Revision as of 16:57, 18 March 2019

Line 1:

{{more footnotes|date=October 2010}}

<br>

<gallery>

In [[computing]], [[Intel]]'s '''Advanced Programmable Interrupt Controller''' ('''APIC''') is a family of [[interrupt controller]]s. As its name suggests, the APIC is more advanced than Intel's [[8259]] [[Programmable Interrupt Controller]] (PIC), particularly enabling the construction of [[multiprocessor]] systems. It is one of several architectural designs intended to solve interrupt routing efficiency issues in multiprocessor computer systems.

_{_{Subscript text}_{_{Subscript text}_{_{Subscript text}_{_{Subscript text}}}}}

</gallery>

Inystems. It is one of several architectural designs intended to solve interrupt routing efficiency issues in multiprocessor computer systems.

The APIC is a split architecture design, with a local component (LAPIC) usually integrated into the processor itself, and an optional I/O APIC on a system bus. The first APIC was the 82489DX{{snd}} it was a discrete chip that functioned both as local and I/O APIC. The 82489DX enabled construction of [[symmetric multiprocessor]] (SMP) systems with the [[Intel 486]] and early [[Pentium]] processors; for example, the reference two-way 486 SMP system used three 82489DX chips, two as local APICs and one as I/O APIC. Starting with the [[P54C]] processor, the local APIC functionality was integrated into the Intel processors' silicon. The first dedicated I/O APIC was the Intel 82093AA, which was intended for [[PIIX3]]-based systems.

785uijmk+pök/

17

== Overview ==