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{{Short description|Instruction pipeline}}
{{Use American English|date = March 2019}}
{{No footnotes|date=December 2012}}
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All MIPS, SPARC, and DLX instructions have at most two register inputs. During the decode stage, these two register names are identified within the instruction, and the two registers named are read from the [[register file]]. In the MIPS design, the register file had 32 entries.
At the same time the register file was read, instruction issue logic in this stage determined if the pipeline was ready to execute the instruction in this stage. If not, the issue logic would cause both the Instruction Fetch stage and the Decode stage to stall. On a stall cycle, the stages would prevent their initial flip-flops from accepting new bits.
If the instruction decoded was a branch or jump, the target address of the branch or jump was computed in parallel with reading the register file. The branch condition is computed after the register file is read, and if the branch is taken or if the instruction is a jump, the PC predictor in the first stage is assigned the branch target, rather than the incremented PC that has been computed. It should be noted that some architectures made use of the [[Arithmetic logic unit|ALU]] in the Execute stage, at the cost of slightly decrease instruction throughput.
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