Template:Infobox CPU architecture/doc: Difference between revisions

Revision as of 01:44, 13 January 2018

Revision as of 10:56, 29 March 2019

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<pre>

{{Infobox CPU architecture

| name =

| designer =

| bits =

| introduced =

| version =

| design =

| type =

| encoding =

| branching =

| endianness =

| page size =

| extensions =

| open =

| registers predecessor =

| gpr successor =

| fpr registers =

| gpr =

| fpr =

}}

</pre>

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<pre>

{{Infobox CPU architecture

| name = Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM

| designer = Designer of the architecture

| bits = Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit

| introduced = Year introduced

| version = Version/revision of architecture/ISA

| design = Design strategy, e.g. RISC, CISC

| type = Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory

| encoding = Instruction set encoding, e.g. Fixed or Variable

| branching = Branching evaluation, e.g. Condition register, Condition code, Compare and branch

| endianness = Byte ordering, i.e. Little, Big, Bi

| page size = Primary size of page, i.e. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions

| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc

| open = Is the architecture open or not? (as in free or proprietary)

| predecessor = Earlier architecture(s) this one is based on, if it has a separate page

| registers = Number and size of processor registers

| successor = Later architecture(s) based primarily on this one, if it has a separate page

| gpr = Number of general-purpose registers (and size, if not indicated by bits=)

| fpropen = NumberIs ofthe floating-pointarchitecture registersopen (andor size,not? if(as notin indicatedfree byor bits=proprietary)

| registers = Number and size of processor registers

| gpr = Number of general-purpose registers (and size, if not indicated by bits=)

| fpr = Number of floating-point registers (and size, if not indicated by bits=)

}}

</pre>

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| open = Yes

| gpr = 31 (G0 = 0; non-global registers use [[register window]]s)

| fpr = 32

}}

<pre>

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; extensions: ISA extensions, e.g. MMX, SSE, AltiVec

; open: Is the architecture open or not? (as in free or proprietary)

; predecessor: Earlier architecture(s) this one is based on, if it has a separate page

; successor: Later architecture(s) based primarily on this one, if it has a separate page

; registers: Number and size of processor registers

; gpr: Number of general-purpose registers (and size, if not indicated by bits=)