Classic RISC pipeline: Difference between revisions

Revision as of 11:54, 25 April 2019

Revision as of 11:55, 25 April 2019

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===Instruction fetch===

The Instruction [[Cache (computing)|Cache]] on these machines had a latency of one cycle(machine cycle), meaning that if the instruction was in the cache, it would be ready on the next [[clock cycle]]. During the [[Instruction fetch|Instruction Fetch]] stage, a 32-bit instruction was fetched from the cache.

The [[Program Counter]], or PC, is a register that holds the address of the current instruction. It feeds into the PC predictor, which then sends the [[Program Counter]] (PC) to the Instruction Cache to read the current instruction. At the same time, the PC predictor predicts the address of the next instruction by incrementing the PC by 4 (all instructions were 4 bytes long). This prediction was always wrong in the case of a taken branch, jump, or exception (see '''delayed branches''', below). Later machines would use more complicated and accurate algorithms ([[branch prediction]] and [[branch target predictor|branch target prediction]]) to guess the next instruction address.