Field-programmable analog array: Difference between revisions

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== History ==

The term FPAA was first used in 1991 by Lee and Gulak.<ref name="1 Lee and Gulak">{{cite web|url=httphttps://ieeexplore.ieee.org/document/104162/|title=A CMOS Field-programmable analog array," Solid-State Circuits}}</ref> They put forward the concept of CABs that are connected via a routing network and configured digitally. Subsequently, in 1992<ref name="2 Lee and Gulak">{{cite web|url=https://pdfs.semanticscholar.org/54e0/a44d6cfca95ba9dccdf567cf1f828bd2ee0d.pdf|title=Field programmable analogue array based on MOSFET transconductors}}</ref> and 1995<ref name="3 Lee and Gulak">{{cite web|url=https://ieeexplore.ieee.org/document/535521|title=A transconductor-based field programmable analog array}}</ref> they further elaborated the concept with the inclusion of op-amps, capacitors, and resistors. This original chip was manufactured using 1.2&nbsp;µm CMOS technology and operates in the 20&nbsp;kHz range at a power consumption of 80&nbsp;mW.

Pierzchala et al introduced a similar concept named '''electronically-programmable analog circuit''' ('''EPAC''').<ref name="4 Pierzchala">{{cite web|url=httphttps://ieeexplore.ieee.org/document/535520/|title=Current Mode amplifier/integrator for field programmable analog array}}</ref> It featured only a single integrator. However, they proposed a local interconnect [[Network architecture|architecture]] in order to try and avoid the bandwidth limitations.

The '''reconfigurable analog signal processor''' ('''RASP''') and a second version were introduced in 2002 by Hall et al.<ref name="6 Hall">{{cite web|url=https://pdfs.semanticscholar.org/354a/bb6fa51506645957efe5effe18741dba0699.pdf|title=Field Programmable Analog Arrays: A Floating-Gate Approach}}</ref><ref name="7 Hall">{{cite web|url=httphttps://ieeexplore.ieee.org/document/1528675/|title=Large scale field programmable analog arrays for analog signal processing}}</ref> Their design incorporated high-level elements such as second order [[Band-pass filter|bandpass filters]] and 4 by 4 vector matrix multipliers into the CABs. Because of its architecture, it is limited to around 100&nbsp;kHz and the chip itself is not able to support independent reconfiguration.

In 2004 Joachim Becker picked up the [[parallel connection]] of OTAs (operational transconductance amplifiers) and proposed its use in a hexagonal local interconnection architecture.<ref name="8 Becker">{{cite web|url=http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.444.8748&rep=rep1&type=pdf|title=.,"A continuous-time field programmable analog array (FPAA) consisting of digitally reconfigurable GM-cells}}</ref> It did not require a routing network and eliminated switching the signal path that enhances the frequency response.

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<references />

* [httphttps://ieeexplore.ieee.org/document/7374749/ "A Programmable and Configurable Mixed-Mode FPAA SoC"] Jennifer Hasler et al., [[Georgia Tech]], January 7, 2016.

* [http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=205916545 "Analog's Answer to FPGA Opens Field to Masses"] Sunny Bains, ''EE Times'', February 21, 2008. Issue 1510.

* [http://opencircuitdesign.com/~tim/research/fpaa/fpaa.html "Field programmable analog arrays"] Tim Edwards, [[Johns Hopkins University]] project, 1999.