Single-electron transistor: Difference between revisions

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[[File:SET schematic2.jpg|thumb|Schematic of a basic SET and its internal electrical components.]]

A '''single-electron transistor''' ('''SET''') is a sensitive electronic device based on the [[Coulomb blockade]] effect. In this device the electrons flow through a tunnel junction between source/drain to a [[quantum dot]] (conductive island). Moreover, the electrical potential of the island can be tuned by a third electrode, known as the gate, which is capacitively coupled to the island. The conductive island is sandwiched between two tunnel junctions,

<ref>{{cite journal|last1=Mahapatra|first1=S.|last2=Vaish|first2=V.|last3=Wasshuber|first3=C.|last4=Banerjee|first4=K.|last5=Ionescu|first5=A.M.|title=Analytical Modeling of Single Electron Transistor for Hybrid CMOS-SET Analog IC Design|journal=IEEE Transactions on Electron Devices|volume=51|issue=11|year=2004|pages=1772–1782|issn=0018-9383|doi=10.1109/TED.2004.837369}}</ref> which are modeled by a capacitor (<math>C_DC_{\rm D}</math> and <math>C_SC_{\rm S}</math>) and a resistor (<math>R_DR_{\rm D}</math> and <math>R_SR_{\rm S}</math>) in parallel.

== History ==

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When [[David Thouless]] pointed out in 1977 that the size of a conductor, if made small enough, will affect the electronic properties of the conductor, a new subfield of condensed matter physics was started.<ref>{{cite journal |last1=Thouless |first1=David J. |authorlink=David J. Thouless| title=Maximum Metallic Resistance in Thin Wires |journal=Phys. Rev. Lett. |volume=39 |issue=18 |pages=1167-1169 |year=1977 |doi=10.1103/PhysRevLett.39.1167| url=https://link.aps.org/doi/10.1103/PhysRevLett.39.1167}}</ref> The research that followed during the 1980s was known as the mesoscopic physics, based on the submicron-size system investigated.<ref>{{cite journal|last1=Al'Tshuler|first1=Boris L.|last2=Lee|first2=Patrick A.|title=Disordered electronic systems|journal=Physics Today|volume=41|issue=12|year=1988|pages=36-44|doi=10.1063/1.881139}}</ref> This was the starting point of the research related to the single-electron transistor.

The first single-electron transistor based on the Coulomb blockade was reported in 1986 by Soviet scientists {{ill|K. K. Likharev|ru|Лихарев, Константин Константинович}} and D. V. Averin.<ref name=":1">{{Cite journal|last=Averin|first=D. V.|last2=Likharev|first2=K. K.|date=1986-02-01|title=Coulomb blockade of single-electron tunnelingtunnelling, and coherent oscillations in small tunnel junctions|journal=Journal of Low Temperature Physics|language=en|volume=62|issue=3–4|pages=345–373|doi=10.1007/BF00683469|issn=0022-2291|bibcode=1986JLTP...62..345A}}</ref> A couple of years later, T. Fulton and G. Dolan at Bell Labs in the US fabricated and demonstrated how such a device works.<ref>{{cite web|url=https://physicsworld.com/a/single-electron-transistors/|title=Single-electron transistors|date=1998-09-01|access-date=2019-09-17|publisher=Physics World}}</ref> In 1992 [[Marc A. Kastner]] demonstrated the importance of the energy levels of the quantum dot.<ref>{{cite journal|last1=Kastner|first1=M. A.|date=1992-07-01|title=The single-electron transistor|journal=Rev. Mod. Phys.|volume=64|issue=3|pages=849-858|doi=10.1103/RevModPhys.64.849}}</ref> In the late 1990s and early 2000s, Russian physicists S. P. Gubin, V. V. Kolesov, E. S. Soldatov, A. S. Trifonov, V. V. Khanin, G. B. Khomutov, and S. A. Yakovenko were the first ones to ever make a molecule based SET operational at room temperature.<ref>{{cite journal|last1=Gubin|first1=S. P.|last2=Gulayev|first2=Yu V.|last3=Khomutov|first3=G. B.|last4=Kislov|first4=V. V.|last5=Kolesov|first5=V. V.|last6=Soldatov|first6=E. S.|last7=Sulaimankulov|first7=K. S.|last8=Trifonov|first8=A. S.|title=Molecular clusters as building blocks for nanoelectronics: the first demonstration of a cluster single-electron tunnelling transistor at room temperature|doi=10.1088/0957-4484/13/2/311|journal=Nanotechnology|year=2002|pages=185-194|volume=13|issue=2}}.</ref>

== Relevance ==

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The increasing relevance of the [[Internet of things]] and the healthcare applications give more relevant impact to the electronic device power consumption. For this purpose, ultra-low-power consumption is one of the main research topics into the current electronics world. The amazing number of tiny computers used in the day-to-day world, e.g. mobile phones and home electronics; requires a significant power consumption level of the implemented devices. In this scenario, the SET has appeared as a suitable candidate to achieve this low power range with high level of device integration.

Applicable areas are among others: supersensitivesuper-sensitive electrometers, Single-electron spectroscopy, DC current standards, temperature standards, detection of infrared radiation, voltage state logics, charge state logics, programmable single-electron transistor logic. <ref>{{cite journal|last1=Kumar|first1=O.|last2=Kaur|first2=M.|title=Single Electron Transistor: Applications & Problems|journal=International Journal of VLSI Design & Communication Systems|year=2010|volume=1|issue=4|pages=24-29|doi=10.5121/vlsic.2010.1403}}</ref>

== Device ==

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=== Principle ===

[[File:Set schematic.svg|thumb|right|Schematic of a single-electron transistor.]]

[[File:Single electron transistor.svg|thumb|right|Left to right: energy levels of source, island and drain in a single-electron transistor for the blocking state (upper part) and transmitting state (lower part).]]

The SET has, Like the [[field-effect transistor|FET]], three electrodes: source, drain, and a gate. The main technological difference between the transistor types is in the channel concept. While the channel changes from insulated to conductive with applied gate voltage in the FET, the SET is always insulated. The source and drain are coupled through two [[Quantum tunnelling|tunnel junctions]], separated by a metallic or semiconductor-based [[quantum dot|quantum nanodot]] (QD)<ref name="UchidaMatsuzawa2000">{{cite journal|last1=Uchida|first1=Ken|last2=Matsuzawa|first2=Kazuya|last3=Koga|first3=Junji|last4=Ohba|first4=Ryuji|last5=Takagi|first5=Shin-ichi|last6=Toriumi|first6=Akira|title=Analytical Single-Electron Transistor (SET) Model for Design and Analysis of Realistic SET Circuits|journal=Japanese Journal of Applied Physics|volume=39|issue=Part 1, No. 4B|year=2000|pages=2321–2324|issn=0021-4922|doi=10.1143/JJAP.39.2321}}</ref>, also known as the "island". The electrical potential of the QD can be tuned with the capacitively coupled gate electrode to alter the resistance, by applying a positive voltage the QD will change from blocking to non-blocking state and electrons will start tunnelingtunnelling to the QD. This phenomenon is knwon as the [[Coulomb blockade]].

The current, <math>I,</math> from source to drain follows [[Ohm's_law|Ohm's law]] when <math>V_{\rm SD}</math> is applied, and it equals <math>\tfrac{V_{\rm SD}}{R},</math> where the main contribution of the resistance, <math>R,</math> comes from the tunnelling effects when electrons move from source to QD, and from QD to drain. <math>V_{\rm G}</math> regulates the resistance of the QD, which regulates the current. This is the exact same behaviorbehaviour as in regular FETs. However, when moving away from the macroscopic scale, the quantum effects will affect the current, <math>I.</math>

In the blocking state all lower energy levels are occupied at the QD and no unoccupied level is within tunnelling range of electrons originating from the source (green 1.). When an electron arrives at the QD (2.) in the non-blocking state it will fill the lowest available vacant energy level, which will raise the energy barrier of the QD, taking it out of tunnelling distance once again. The electron will continue to tunnel through the second tunnel junction (3.), afterwhichafter which it scatters inelastically and reaches the drain electrode Fermi level (4.).

The energy levels of the QD are evenly spaced with a separation of <math>\Delta E.</math> This gives rise to a self-capacitance <math>C</math> of the island, defined as: <math>C=\tfrac{e^2}{\Delta E}.</math> To achieve the Coulomb blockade, three criteria need to be met: <ref>{{cite book

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# The bias voltage must be lower than the [[elementary charge]] divided by the self-capacitance of the island: <math>V_\text{bias} < \tfrac{e}{C}</math>

# The thermal energy in the source contact plus the thermal energy in the island, i.e. <math>k_{\rm B}T,</math> must be below the charging energy: <math>k_{\rm B}T \ll \tfrac{e^2}{2C},</math> otherwise the electron will be able to pass the QD via thermal excitation.

# The tunnelingtunnelling resistance, <math>R_{\rm t},</math> should be greater than <math>\tfrac{h}{e^2},</math> which is derived from Heisenberg's [[uncertainty principle]]. <ref>{{cite thesis|last=Wasshuber|first=Christoph|title=About Single-Electron Devices and Circuits|date=1997|degree=|publisher=Vienna University of Technology|url=http://www.iue.tuwien.ac.at/phd/wasshuber/node20.html|doi=|type=Ph.D.|chapter=2.5 Minimum Tunnel Resistance for Single Electron Charging}}</ref> <math>\Delta E \Delta t = \left( \tfrac{e^2}{2C} \right) (R_{\rm T} C) > h,</math> where <math>(R_{\rm T} C)</math> corresponds to the tunnelingtunnelling time <math>\tau</math> and is shown as <math>C_{\rm S} R_{\rm S}</math> and <math>C_{\rm D} R_{\rm D}</math> in the schematic figure of the internal electrical components of the SET. The time (<math>\tau</math>) of electron tunnelling through the barrier is assumed to be negligibly small in comparison with the other time scales. This assumption is valid for tunnel barriers used in single-electron devices of practical interest, where <math>\tau \approx 10^{-15} \text{s}.</math>

If the resistance of all the tunnel barriers of the system is much higher than the quantum resistance <math>R_{\rm t} = \tfrac{h}{e^2} = 25.813~\text{k}\Omega,</math> it is enough to confine the electrons to the island, and it is safe to ignore coherent quantum processes consisting of several simultaneous tunnelling events, i.e. co-tunnelling.

=== Theory ===

The background charge of the dielectric surrounding the QD is indicated by <math>q_0</math>. <math>n_{\rm S}</math> and <math>n_{\rm D}</math> denote the number of electrons tunnelling through the two tunnel junctions and the total number of electrons is <math>n</math>. The corresponding charges at the tunnel junctions can be written as:

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<math>q = q_{\rm D} - q_{\rm S} + q_0 = -ne + q_0,</math>

where <math>C_{\rm S}</math> and <math>C_{\rm D}</math> are the parasitic leakage capacities of the tunnel junctions. Given the bias voltage, <math>V_bV_{\rm bias} = V_{\rm S} + V_{\rm D},</math> you can solve the voltages at the tunnel junctions:

<math>V_{\rm S} = \frac{C_{\rm D} V_b + ne - q_0}{C_{\rm S} + C_{\rm D}},</math>

<math>V_{\rm DS} = \frac{C_{\rm SD} V_bV_{\rm -bias} + ne +- q_0}{C_{\rm S} + C_{\rm D}}.,</math>

<math>V_{\rm SD} = \frac{C_{\rm DS} V_bV_{\rm +bias} - ne -+ q_0}{C_{\rm S} + C_{\rm D}},.</math>

The electrostatic energy of a double-connected tunnel junction (like the one in the schematical picture) will be

<math>E_C = \frac{q_{\rm S}^2}{2 C_{\rm S}} + \frac{q_{\rm D}^2}{2 C_{\rm D}} = \frac{C_{\rm S} C_{\rm D} V_bV_{\rm bias}^2 + (ne - q_0)^2}{2(C_{\rm S} + C_{\rm D})}.</math>

The work performed during electron tunnelling through the first and second transitions will be:

<math>W_{\rm S} = \frac{n_{\rm S} e V_bV_{\rm bias} C_{\rm D}}{C_{\rm S} + C_{\rm D}},</math>

<math>W_{\rm D} = \frac{n_{\rm D} e V_b C_{\rm S}}{C_{\rm S} + C_{\rm D}}.</math>

<math>W_{\rm D} = \frac{n_{\rm D} e V_bV_{\rm bias} C_{\rm S}}{C_{\rm S} + C_{\rm D}}.</math>

Given the standard definition of free energy in the form:

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where <math>E_{\rm tot} = E_C = \Delta E_F + E_N,</math> we find the free energy of a SET as:

<math>F(n, n_{\rm S}, n_{\rm D}) = E_C - W = \frac{1}{C_{\rm S} + C_{\rm D}} \left( \frac{1}{2} C_{\rm S} C_{\rm D} V_bV_{\rm bias}^2 + (ne - q_0)^2 + e V_bV_{\rm bias} C_{\rm S} n_{\rm D} + C_{\rm D} n_{\rm S} \right).</math>

For further consideration, it is necessary to know the change in free energy at zero temperatures at both tunnel junctions:

<math>\Delta F_{\rm S}^{\pm} = F(n \pm 1, n_{\rm S} \pm 1, n_{\rm D}) - F(n, n_{\rm S}, n_{\rm D}) = \frac{e}{C_{\rm S} + C_{\rm D}} \left( \frac{e}{2} \pm (V_bV_{\rm bias} C_{\rm D} + ne - q_0) \right),</math>

<math>\Delta F_{\rm D}^{\pm} = F(n \pm 1, n_{\rm S}, n_{\rm D} \pm 1) - F(n, n_{\rm S}, n_{\rm D}) = \frac{e}{C_{\rm S} + C_{\rm D}} \left( \frac{e}{2} \pm (V_bV_{\rm bias} C_{\rm S} + ne - q_0) \right),</math>

The probability of a tunnel transition will be high when the change in free energy is negative. The main term in the expressions above determines a positive value of <math>\Delta F</math> as long as the applied voltage <math>V_bV_{\rm bias}</math> will not exceed the threshold value, which depends on the smallest capacity in the system. In general, for an uncharged QD (<math>n = 0</math> and <math>q_0 = 0</math>) for symmetric transitions (<math>C_{\rm S} = C_{\rm D} = C</math>) we have the condition

<math>V_{\rm th} = \left|V_bV_{\rm bias}\right| \ge \frac{e}{2 C},</math>

The probability of a tunnel transition will be high when the change in free energy is negative. The main term in the expressions above determines a positive value of <math>\Delta F</math> as long as the applied voltage <math>V_b</math> will not exceed the threshold value, which depends on the smallest capacity in the system. In general, for an uncharged QD (<math>n = 0</math> and <math>q_0 = 0</math>) for symmetric transitions (<math>C_{\rm S} = C_{\rm D} = C</math>) we have the condition

<math>V_{\rm th} = |V_b| \ge \frac{e}{2 C},</math>

(that is, the threshold voltage is reduced by half compared with a single transition).

WheWhen the applied voltage is zero, the Fermi level at the metal electrodes will be inside the energy gap. When the voltage increases to the threshold value, tunnelling from left to right occurs, and when the reversed voltage increases above the threshold level, tunnelling from right to left occurs.

Whe the applied voltage is zero, the Fermi level at the metal electrodes will be inside the energy gap. When the voltage increases to the threshold value, tunnelling from left to right occurs, and when the reversed voltage increases above the threshold level, tunnelling from right to left occurs.

The existence of the Coulomb blockade is clearly visible in the [[current-voltage characteristic]] of a SET (a graph showing how the drain current depends on the gate voltage). At low gate voltages (in absolute value), the drain current will be zero, and when the voltage increases above the threshold, the transitions behave like an ohmic resistance (both transitions have the same permeability) and the current increases linearly. It should be noted here that the background charge in a dielectric can not only reduce, but completely block the Coulomb blockade. <math>q_0 = \pm (0.5 + m) e.</math>

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Substituting this value into the formulas found above, we find new values for the voltages at the transitions:

<math>V_{\rm S} = \frac{(C_{\rm D} + C_{\rm G}) V_bV_{\rm bias} - C_{\rm G} V_{\rm G} + ne - q_0}{C_{\rm S} + C_{\rm D}},</math>

<math>V_{\rm D} = \frac{C_{\rm S} V_b + C_{\rm G} V_{\rm G} - ne + q_0}{C_{\rm S} + C_{\rm D}},</math>

<math>V_{\rm D} = \frac{C_{\rm S} V_bV_{\rm bias} + C_{\rm G} V_{\rm G} - ne + q_0}{C_{\rm S} + C_{\rm D}},</math>

The electrostatic energy should include the energy stored on the gate capacitor, and the work performed by the voltage on the gate should be taken into account in the free energy:

<math>\Delta F_{\rm S}^{\pm} = \frac{e}{C_{\rm S} + C_{\rm D}} \left( \frac{e}{2} \pm V_bV_{\rm bias}(C_{\rm D} + C_{\rm G}) - V_{\rm G} C_{\rm G} + ne + q_0 \right),</math>

<math>\Delta F_{\rm D}^{\pm} = \frac{e}{C_{\rm S} + C_{\rm D}} \left( \frac{e}{2} \pm V_bV_{\rm bias} C_{\rm S} + V_{\rm G} C_{\rm G} - ne + q_0 \right).</math>

At zero temperatures, only transitions with negative free energy are allowed: <math>\Delta F_{\rm S} < 0</math> or <math>\Delta F_{\rm D} < 0</math>. These conditions can be used to find areas of stability in the plane <math>V_bV_{\rm bias} - V_{\rm G}.</math>

With increasing voltage at the gate electrode, when the supply voltage is maintainted below the voltage of the Coulomb blockade (i.e. <math>V_bV_{\rm bias} < \tfrac{e}{C_{\rm S} + C_{\rm D}}</math>), the drain output current will oscillate with a period <math>\tfrac{e}{C_{\rm S} + C_{\rm D}}.</math> These areas correspond to failures in the field of stability. It should be noted here that the oscillations of the tunnelling current occur in time, and the oscillations in two series-connected junctions have a periodicity in the gate control voltage. The thermal broadening of the oscillations increases to a large extent with increasing temperature.

At zero temperatures, only transitions with negative free energy are allowed: <math>\Delta F_{\rm S} < 0</math> or <math>\Delta F_{\rm D} < 0</math>. These conditions can be used to find areas of stability in the plane <math>V_b - V_{\rm G}.</math>

=== Temperature Dependencedependence ===

With increasing voltage at the gate electrode, when the supply voltage is maintainted below the voltage of the Coulomb blockade (i.e. <math>V_b < \tfrac{e}{C_{\rm S} + C_{\rm D}}</math>), the drain output current will oscillate with a period <math>\tfrac{e}{C_{\rm S} + C_{\rm D}}.</math> These areas correspond to failures in the field of stability. It should be noted here that the oscillations of the tunnelling current occur in time, and the oscillations in two series-connected junctions have a periodicity in the gate control voltage. The thermal broadening of the oscillations increases to a large extent with increasing temperature.

=== Temperature Dependence ===

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Various materials have successfully been tested when creating single-electron transistors. However, temperature is a huge factor limiting implementation in available electronical devices. Most of the metallic-based SETs only work at extremely low temperatures.

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The island capacitance is a function of the QD size, and QD <= 3 nm is preferrable when aiming for operation at room temperature. This in turn puts huge restraints on the manufacturability of integrated circuits because of reproducability issues.

=== CMOS Compatibilitycompatibility ===

=== CMOS Compatibility ===

[[File:SETFET schematic.jpg|thumb|Hybrid SET-FET circuit.]]

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The EU funded project IONS4SET (#688072)<ref>{{cite web|url=http://www.ions4set.eu|title=IONS4SET Website|access-date=2019-09-17}}</ref> looks for the manufacturability of SET-FET circuits operative at room temperature. The main goal of this project is to design a SET-manufacturability process-flow for large-scale operations seeking to extend the use of the hybrid Set-CMOS architectures. To assure room temperature operation, single dots of diameters below 5 nm have to be fabricated and located between source and drain with tunnel distances of a few nanometers <ref name="KlupfelBurenkov2016">{{cite journal|last1=Klupfel|first1=F. J.|last2=Burenkov|first2=A.|last3=Lorenz|first3=J.|title=Simulation of silicon-dot-based single-electron memory devices|year=2016|pages=237–240|doi=10.1109/SISPAD.2016.7605191}}</ref>. Up to now there is no reliable process-flow to manufacture a hybrid SET-FET circuit operative at room temperature. In this context, this EU project explores a more feasible way to manufacture the SET-FET circuit by using pillar dimensions of approximately 10 nm <ref>ref name="Xu2019">{{cite arXiv |arxiv=1906.09975v2}}</ref>.

== See also ==

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* [[MOSFET]]

* [[Transistor model]]

== References ==

{{reflist}}

[[Category:Nanoelectronics]]