FPGA prototyping: Difference between revisions

Revision as of 10:53, 15 August 2019

Revision as of 03:00, 29 September 2019

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==Why prototyping is important==

#Running a SoC design on FPGA prototype is a reliable way to ensure that it is functionally correct. This is compared to designers only relying on [[Electronic circuit simulation|software simulations]] to verify that their hardware design is sound. About a third of all current SoC designs are fault-free during first silicon pass, with nearly half of all re-spins caused by functional logic errors.<ref name ="soc">{{Cite web |url=http://www.soccentral.com/results.asp?CatID=596&EntryID=30794 |title=Archived copy |access-date=October 9, 2012 |archive-url=https://archive.is/20130202104923/http://www.soccentral.com/results.asp?CatID=596&EntryID=30794 |archive-date=February 2, 2013 |dead-url-status=yesdead }}</ref> A single prototyping platform can provide verification for hardware, firmware, and application software design functionality before the first silicon pass.<ref>{{Cite web|url=http://www.tayden.com/publications/Nanometer%20Prototyping.pdf|title=Nanometer prototyping|last=Rittman|first=Danny|date=2006-01-05|website=Tayden Design|archive-url=|archive-date=|dead-url=|access-date=2018-10-07}}</ref>

#[[Time to market|Time-to-Market]] (TTM) is reduced from FPGA prototyping: In today's technological driven society, new products are introduced rapidly, and failing to have a product ready at a given [[market window]] can cost a company a considerable amount of [[revenue]].<ref name="reason">{{Cite web|url=http://www.design-reuse.com/articles/13550/fpga-prototyping-to-structured-asic-production-to-reduce-cost-risk-ttm.html|title=FPGA Prototyping to Structured ASIC Production to Reduce Cost, Risk & TTM|website=Design And Reuse|access-date=2018-10-07}}</ref> If a product is released too late of a market window, then the product could be [[Obsolescence|rendered useless]], costing the company its investment capital in the product. After the design process, FPGAs are ready for production, while [[Standard cell|standard cell ASICs]] take more than six months to reach production.<ref name = reason/>

#Development Cost: Development cost of 90-nm ASIC/SoC design tape-out is around $20 million, with a mask set costing over $1 million alone.<ref name= soc/> Development costs of 45-nm designs are expected to top $40 million. With increasing cost of mask sets, and the continuous decrease of IC size, minimizing the number of re-spins is vital to the development process.

==Design for prototyping==

'''Design for Prototyping'''<ref>{{cite web|url=http://www.newelectronics.co.uk/electronics-technology/prototyping-system-designs-on-fpgas/32395/|title=Prototyping System Designs on FPGAs|last=|first=|date=2011-03-22|website=|publisher=New Electronics|archive-url=|archive-date=|dead-url=|accessdate=2011-03-22}}</ref> ('''DFP''') refers to designing systems that are amenable to [[prototyping]]. Many of the obstacles facing development teams who adopt FPGA prototypes can be distilled down to three "laws":

* SoCs are larger than FPGAs

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Due to increased circuit complexity, and time-to-market shrinking, the need for verification of application-specific-integrated-circuit (ASIC) and system-on-chip (SoC) designs is growing. Hardware platforms are becoming more prominent amongst verification engineers due to the ability to test system designs at-speed with on-chip bus clocks, as compared to simulation clocks which may not provide an accurate reading of system behavior.<ref>{{Cite news|url=http://www.eejournal.com/archives/articles/20110825-mathworks/|title=Best Practices for FPGA Prototyping of MATLAB and Simulink Algorithms|date=2011-08-25|work=EEJournal|access-date=2018-10-08|language=en-US}}</ref> These multi-million gate designs usually are placed in a multi-FPGA prototyping platform with six or more FPGAs, since they are unable to fit entirely onto a single FPGA. The fewer number of FPGAs the design has to be partitioned to reduces the effort from the design engineer.<ref name= Aldec/> To the right is a picture of a FPGA-based prototyping platform utilizing a dual-FPGA configuration. [[File:Aldec HES7 ASIC Prototyping Platform.jpg|thumb|alt=Aldec FPGA-based prototyping platform with dual FPGA configuration.|Aldec's HES-7 ASIC prototyping solution]]

System RTL designs or netlists will have to be partitioned onto each FPGA to be able to fit the design onto the prototyping platform.<ref>{{Cite web |url=http://www.electronicsweekly.com/Articles/20/12/2007/42539/fpga-prototyping-its-about-the-software.htm |title=Archived copy |access-date=October 9, 2012 |archive-url=https://archive.is/20130122001104/http://www.electronicsweekly.com/Articles/20/12/2007/42539/fpga-prototyping-its-about-the-software.htm |archive-date=January 22, 2013 |dead-url-status=yesdead }}</ref> This introduces new challenges for the engineer since manual partitioning requires tremendous effort and frequently results in poor speed (of the design under test).<ref name ="Aldec">[http://www.aldec.com/en/downloads/private/284 "Aldec and Xilinx Co-Authored White Paper "HES-7 ASIC Prototyping"], Registration Required</ref> If the number or partitions can be reduced or the entire design can be placed onto a single FPGA, the implementation of the design onto the prototyping platform becomes easier.

===Balance FPGA Resources While Creating Design Partitions===