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{{cleanup|December 2006}}
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The name derives from analogy with the regular pumping of blood by the heart. In [[computer architecture]], a '''systolic array''' is an arrangement of [[data processing unit]]s ([[DPU]]s, almost similar to [[central processing unit]]s ([[CPU]])s, but without a [[Program counter]], since operation is transport-triggered, i. e. by the arrival of a data object, like known also from [[Transport Triggered Architectures]]), in an [[array]] (often rectangular) where data flows across the array between neighbours, usually with different data flowing in different directions. The [[Data stream]]s entering and leaving the ports of the array are generated by [[auto-sequencing memory]] units (ASMs). Each ASM includes a [[Data counter]]. In [[Embedded System]]s a data stream may also be inputted from and/or outputted to an external source.
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Each processor at each step takes in data from one or more neighbours (e.g. North and West), processes it and, in the next step, outputs results in the opposite direction (South and East).
An example of a systolic [[algorithm]] might be [[
Because the classical synthesis methods (algebraic, i. e. projection-based synthesis), yielding only uniform [[Data Path Unit|DPU]] arrays permitting only linear pipes, systolic arrays could be used only to implement applications with regular data dependencies. By using [[simulated annealing]] instead, [[Rainer Kress]] came up with the [[super systolic array]], a generalization of the systolic array not being restricted to regular data dependencies.
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