Cache hierarchy: Difference between revisions

Revision as of 13:57, 27 October 2019

Revision as of 19:21, 15 December 2019

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=== Shared versus private ===

[[File:Shared private.png|thumb|Cache organization with L1 private and L2 and L3 shared|alt=Three CPUs each have private on-chip L1 caches but share the off-chip L2, L3, and main memory.]]

A private cache is assigned to one particular core in a processor, and cannot be accessed by any other cores. In some architectures, each core has its own private cache; this creates the risk of duplicate blocks in a system's cache architecture, which results in reduced capacity utilization. However, this type of design choice in a multi-layer cache architecture can also lendbe itselfgood tofor a lower data-access latency.<ref name=":0" /><ref>{{Cite web|url=https://software.intel.com/en-us/articles/software-techniques-for-shared-cache-multi-core-systems|title=Software Techniques for Shared-Cache Multi-Core Systems|last=|first=|date=|website=|publisher=|access-date=}}</ref><ref>{{Cite web|url=http://hpcaconf.org/hpca13/papers/002-dybdahl.pdf|title=An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors|last=|first=|date=|website=|publisher=|access-date=|archive-url=https://web.archive.org/web/20161019143428/http://hpcaconf.org/hpca13/papers/002-dybdahl.pdf|archive-date=2016-10-19|url-status=dead}}</ref>

A shared cache is a cache which can be accessed by multiple cores.<ref>Akanksha Jain; Calvin Lin; 2019. Cache Replacement Policies. Morgan & Claypool Publishers. p. 45. {{ISBN|978-1-68173-577-1}}.</ref> Since it is shared, each block in the cache is unique and therefore has a larger hit rate as there will be no duplicate blocks. However, data-access latency can increase as multiple cores try to access the same cache.<ref>David Culler; Jaswinder Pal Singh; Anoop Gupta; 1999. Parallel Computer Architecture: A Hardware/Software Approach. Gulf Professional Publishing. p. 436. {{ISBN|978-1-55860-343-1}}.</ref>