VESA Local Bus: Difference between revisions

Revision as of 07:26, 22 September 2019

Revision as of 07:49, 31 December 2019

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[[File:KL ATI Mach 64 VLB.jpg|thumb|left|upright=1.5|An ATI MACH64 [[SVGA]] VLB graphics card]]

In the early 1990s, the [[I/O]] bandwidth of the prevailing ISA bus, 8.33 MB/s for standard 16 bit 8.33 MHz slots, had become a critical bottleneck to PC video and graphics performance. The need for faster graphics was driven by increased adoption of [[graphical user interface]]s in PC operating systems. While IBM did produce a viable successor to ISA with the [[Micro Channel Architecture]] offering a bandwidth of 66 MB/s, it failed in the market due to IBM's requirement to license and payment of licensing fees by hardware manufacturers to use it. While an extension of the royalty-free ISA bus in the form of [[Extended Industry Standard Architecture|EISA]] open standard was developed to counter MCA, it's bandwidth of 33.32 MB/s was unable to offer enough improvement over ISA to meet the significant increase in bandwidth desired for graphics.

Thus for a short time, a market opening occurred where video card manufacturers and motherboard chipset makers created their own proprietary implementations of [[local bus]]es to provide graphics cards direct access to the processor and system memory. This avoided the limitations of the ISA bus while being less costly than a "licensed IBM MCA machine". It is important to note that at the time a migration to an MCA architecture machine from an ISA one was not insubstantial. MCA machines generally did not offer ISA slots, thus a migration to MCA architecture meant that any prior investment in ISA cards was made unusable. Additionally, makers of MCA-compatible cards were subject to IBM's licensing fees, which combined with MCA's greater technical requirements and expense to implement (which in itself is not bad: MCA required peripheral cards to not just be "passive" members and made cards active participants in increasing system performance) it did have the effect of making an MCA version of a peripheral card significantly more expensive than its ISA counterpart.

So while these ad-hoc manufacturer-specific solutions where effective, they were not standardized, and there were no provisions for providing interoperability. This drew the attention of the [[VESA]] consortium and resulted in a proposal for a voluntary and royalty-free local bus standard in 1992.<ref>Richter, Jake. [https://books.google.com/books?id=XlEEAAAAMBAJ&pg=PA66 "Local-bus architecture: A little-understood, much-cited graphics technology"], "InfoWorld", May 18, 1992, accessed March 9, 2011.</ref> An additional benefit from this standardization (beyond the primary goal of greater graphics card performance) was that other devices could also be designed to utilize the performance offered from VLB; notably, mass-storage controllers were offered for VLB, providing increased hard-disk performance. VLB bandwidth depended on the CPU's bus speed: It started at 100 MB/s for CPUs with a 25 MHz bus, increased to 133 MB/s at 33 MHz and 160 MB/s at 40 MHz, and reached 200 MB/s at 50 MHz.

== Implementation ==

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==Limitations==

[[File:Vlb.jpg|thumb|right|upright=1.5|Computer [[motherboard]] with 7 [[Industry Standard Architecture|ISA]] slots of various feature levels. One Sixis a short 8-bit slot, six are 16-bit ISA (longer{{snd}} with middle black sections), three additionally have a VLB slot (leftmost brown sections). A card installed in this boardmotherboard would have its mounting bracket on the right, which normally would be the "back" of the computer case.]]

The VESA Local Bus was designed as a [[wiktionary:stopgap|stopgap]] solution to the problem of the ISA bus's limited [[Bandwidth (computing)|bandwidth]]. As such, one requirement for VLB to gain industry adoption was that it had to be a minimal burden for manufactures to implement, in terms of board re-design and component costs; otherwise, manufacturers would not have been convinced to change from their own proprietary solutions. As VLB fundamentally tied a card directly to the 486 processor bus with minimal intermediary logic (reducing logic design and component costs), timing and arbitration duties were strongly dependent on the cards and CPU.<ref name="Infinite expansion" />

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! Clock

| 486SX-25: 25&nbsp;MHz<br> 486DX2-50: 25&nbsp;MHz<br> 486DX-33: 33&nbsp;MHz<br>486DX2-66: 33&nbsp;MHz<br>486DX4-100: 33&nbsp;MHz<br>486DX-40: 40&nbsp;MHz<br>486DX2-80: 40&nbsp;MHz<br>486DX4-120: 40&nbsp;MHz<br>5x86@133&nbsp;MHz: 33&nbsp;MHz<br>5x86@160&nbsp;MHz: 40&nbsp;MHz<br>486DX-50: 50&nbsp;MHz (out of specification)

|-

!Bandwidth

|25 MHz: 100 MB/s

33 MHz: 133 MB/s

40 MHz: 160 MB/s

50 MHz: 200 MB/s (out of specification)

|}