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[[File:Page Tables (5 levels).svg|thumb|A diagram of five levels of paging]]
'''Intel 5-level paging''', referred to simply as ''5-level paging'' in [[Intel]] documents, is a possible future processor extension for the [[x86-64]] line of processors.<ref name="intel-white-paper">{{Cite web|url=https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf|title=5-Level Paging and 5-Level EPT|publisher=Intel Corporation|date=May 2017}}</ref>{{Rp|11}} It extends the size of [[virtual address]]es from 48 bits to 57 bits, increasing the addressable [[virtual memory]] from 256 [[terabyte|terabytes]] to 128 [[petabyte|petabytes]].<ref group=NB>{{BDprefix|p=B}}</ref> While the technical document describing the extension is a [[white paper]], stating ''"do not finalize a design with this information",'' support for the extension has already been implemented in the [[Linux kernel]].<ref>{{Cite news|url=https://www.zdnet.com/article/first-linux-4-14-release-adds-very-core-features-arrives-in-time-for-kernels-26th-birthday/|title=First Linux 4.14 release adds "very core" features, arrives in time for kernel's 26th birthday {{!}} ZDNet|last=Tung|first=Liam|work=ZDNet|access-date=2018-04-25|language=en}}</ref>
