Non-volatile random-access memory: Difference between revisions

Revision as of 19:00, 9 January 2020

Revision as of 22:58, 16 January 2020

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'''Non-volatile random-access memory''' ('''NVRAM''') is [[random-access memory]] that is non-volatile. This is in contrast to [[dynamic random-access memory]] (DRAM) and [[static random-access memory]] (SRAM), which both maintain data only for as long as power is applied.

Currently, the best-known form of both NV-RAM and [[EEPROM]] memory is [[flash memory]]. Some drawbacks to flash memory include the requirement to write it in larger blocks than many computers can automatically address, and the relatively limited longevity of flash memory due to its finite number of write-erase cycles (as of January 2010 most consumer flash products can withstand only around 100,000 rewrites before memory begins to deteriorate){{Citation needed}}. Another drawback is the performance limitations preventing flash from matching the response times and, in some cases, the random addressability offered by traditional forms of RAM. Several newer technologies are attempting to replace flash in certain roles, and some even claim to be a truly [[universal memory]], offering the performance of the best SRAM devices with the non-volatility of flash.<ref>"[https://www.academia.edu/6988421/A_Survey_Of_Architectural_Approaches_for_Managing_Embedded_DRAM_and_Non-volatile_On-chip_Caches A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches]", Mittal et al., IEEE TPDS, 2014.</ref> As of June 2018 these alternatives have not yet become mainstream.

Development is going on for the use of non-volatile memory chips as a system's main memory, as [[persistent memory]]. Known as [[NVDIMM#Types|NVDIMM-P]], it is expected to be released in 2020.<ref>{{cite press release|url=https://www.jedec.org/news/pressreleases/jedec-ddr5-nvdimm-p-standards-under-development|title=JEDEC DDR5 & NVDIMM-P Standards Under Development|date=2017-03-30|publisher=[[JEDEC]]}}</ref><ref>{{cite press release|url=https://www.jedec.org/news/pressreleases/jedec-hold-workshops-ddr5-lpddr5-nvdimm-p-standards|title=JEDEC to Hold Workshops for DDR5, LPDDR5 & NVDIMM-P Standards|date=2019-09-05|publisher=JEDEC}}</ref>