Advanced Programmable Interrupt Controller: Difference between revisions

Revision as of 10:28, 24 December 2019

Revision as of 01:26, 9 February 2020

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The x2APIC now uses 32 bits to address CPUs, allowing to address up to 2³² − 1 CPUs using the physical destination mode. The logical destination mode now works differently and introduces clusters; using this mode, one can address up to 2²⁰ − 16 processors. The x2APIC architecture also provides backward compatibility modes to the original Intel APIC Architecture (introduced with the [[Pentium]]/[[P6 (microarchitecture)|P6]]) and with the xAPIC architecture (introduced with the [[Pentium 4]]).

The improved interface reduces the number of needed APIC register access for sending [[Inter-processor interrupt]]s (IPIs). Because of this advantage, [[QEMUKVM]] can and does emulate the x2APIC for older processors that do not physically support it, and this support is exposed from [[QEMU]] going back to [[Conroe (microprocessor)|Conroe]] and even for AMD [[Opteron]] G-series processors (neither of which natively support x2APIC).<ref>{{cite web|url=https://lists.gnu.org/archive/html/qemu-devel/2013-07/msg03756.html|title=Re: [Qemu-devel] [Question] why x2apic's set by default without host sup|website=lists.gnu.org}}</ref><ref>{{cite web|url=http://lists.nongnu.org/archive/html/qemu-devel/2014-01/msg02441.html|title=[Qemu-devel] [PATCH] target-i386: enable x2apic by default on more recen|website=lists.nongnu.org}}</ref>

[[APICv]] is the Intel's brand name for [[hardware virtualization]] support aimed at reducing interrupt overhead in guests. APICv was introduced in the [[Ivy Bridge-EP]] processor series, which is sold as Xeon E5-26xx v2 (launched in late 2013) and as Xeon E5-46xx v2 (launched in early 2014).<ref>http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-intel-vt-feat-nakajima.pdf</ref><ref>{{cite web|url=https://software.intel.com/en-us/blogs/2013/12/17/apic-virtualization-performance-testing-and-iozone|title=APIC Virtualization Performance Testing and Iozone* - Intel® Software|website=software.intel.com}}</ref><ref>http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/xeon-e5-4600-v2-brief.pdf</ref> AMD announced a similar technology called [[Advanced Virtual Interrupt Controller|AVIC]],<ref>Wei Huang, [http://www.slideshare.net/xen_com_mgr/introduction-of-amd-virtual-interrupt-controller Introduction of AMD Advanced Virtual Interrupt Controller], XenSummit 2012</ref><ref>http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-interrupt-virt-kvm-roedel.pdf</ref> it is available family [[Excavator (microarchitecture)|15h models 6Xh (Carrizo) processors]] and newer.<ref>{{cite web|url=https://www.mail-archive.com/[e-mail]/msg81719.html|title=[Xen-devel] [RFC PATCH 0/9] Introduce AMD SVM AVIC|website=www.mail-archive.com}}</ref>