The term FPAA was first used in 1991 by Lee and Gulak.<ref name="1 Lee and Gulak">{{cite web|url=https://ieeexplore.ieee.org/document/104162/|title=A CMOS Field-programmable analog array," Solid-State Circuits|doi=10.1109/4.104162}}</ref> They put forward the concept of CABs that are connected via a routing network and configured digitally. Subsequently, in 1992<ref name="2 Lee and Gulak">{{cite web|url=https://pdfs.semanticscholar.org/54e0/a44d6cfca95ba9dccdf567cf1f828bd2ee0d.pdf|title=Field programmable analogue array based on MOSFET transconductors}}</ref> and 1995<ref name="3 Lee and Gulak">{{cite web|url=https://ieeexplore.ieee.org/document/535521book|title=A transconductor-based field programmable analog array|chapter=A transconductor-based field-programmable analog array|doi=10.1109/ISSCC.1995.535521|isbn=0-7803-2495-1|year=1995|last1=Lee|first1=E.K.F.|last2=Gulak|first2=P.G.|pages=198–199}}</ref> they further elaborated the concept with the inclusion of op-amps, capacitors, and resistors. This original chip was manufactured using 1.2 µm CMOS technology and operates in the 20 kHz range at a power consumption of 80 mW.
Pierzchala et al introduced a similar concept named '''electronically-programmable analog circuit''' ('''EPAC''').<ref name="4 Pierzchala">{{cite web|url=https://ieeexplore.ieee.org/document/535520/book|title=Current Mode amplifier/integrator for field programmable analog array|chapter=Current-mode amplifier/Integrator for a field-programmable analog array|doi=10.1109/ISSCC.1995.535520|isbn=0-7803-2495-1|year=1995|last1=Pierzchala|first1=E.|last2=Perkowski|first2=M.A.|last3=Van Halen|first3=P.|last4=Schaumann|first4=R.|pages=196–197}}</ref> It featured only a single integrator. However, they proposed a local interconnect [[Network architecture|architecture]] in order to try and avoid the bandwidth limitations.
The '''reconfigurable analog signal processor''' ('''RASP''') and a second version were introduced in 2002 by Hall et al.<ref name="6 Hall">{{cite web|url=https://pdfs.semanticscholar.org/354a/bb6fa51506645957efe5effe18741dba0699.pdf|title=Field Programmable Analog Arrays: A Floating-Gate Approach|year=2002}}</ref><ref name="7 Hall">{{cite web|url=https://ieeexplore.ieee.org/document/1528675/journal|title=Large scale field programmable analog arrays for analog signal processing|doi=10.1109/TCSI.2005.853401|year=2005|last1=Hall|first1=T.S.|last2=Twigg|first2=C.M.|last3=Gray|first3=J.D.|last4=Hasler|first4=P.|last5=Anderson|first5=D.V.|journal=IEEE Transactions on Circuits and Systems I: Regular Papers|volume=52|issue=11|pages=2298–2307}}</ref> Their design incorporated high-level elements such as second order [[Band-pass filter|bandpass filters]] and 4 by 4 vector matrix multipliers into the CABs. Because of its architecture, it is limited to around 100 kHz and the chip itself is not able to support independent reconfiguration.
In 2004 Joachim Becker picked up the [[parallel connection]] of OTAs (operational transconductance amplifiers) and proposed its use in a hexagonal local interconnection architecture.<ref name="8 Becker">{{cite journal|title=.,"A continuous-time field programmable analog array (FPAA) consisting of digitally reconfigurable GM-cells|citeseerx = 10.1.1.444.8748}}</ref> It did not require a routing network and eliminated switching the signal path that enhances the frequency response.
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In 2005 Fabian Henrici worked with Joachim Becker to develop a switchable and invertible OTA which doubled the maximum FPAA bandwidth.<ref name="9 Becker">{{cite journal|title=A Continuous-Time Hexagonal Field-Programmable Analog Array in 0.13 µm CMOS with 186MHz GBW|citeseerx = 10.1.1.444.8748}}</ref> This collaboration resulted in the first manufactured FPAA in a [[130 nanometer|0.13 µm]] [[CMOS]] technology.
In 2016 Dr. Jennifer Hasler from Georgia Tech. university designed a FPAA System on Chip that uses analog technology to achieve unprecedented power and size reductions.<ref name="11 Hasler">{{cite web|url=https://ieeexplore.ieee.org/document/7374749/|title=A Programmable and Configurable Mixed-Mode FPAA SoC, Jennifer Hasler et al., Georgia Tech., January 7, 2016|doi=10.1109/TVLSI.2015.2504119}}</ref>
